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In advanced field plate trench power MOSFETs (FP-MOSFETs), narrow and deep trench causes lots of challenges for process integration. Especially, process optimization for silicon in trench is the most crucial. Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. Therefore, we studied new process optimization of FP-MOSFETs with sequential phosphorus-doped silicon method, compared with “conventional” phosphorus diffusion method. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. Inserting $800{^\circ }\text{C}$ annealing before $1000{^\circ }\text{C}$ annealing contributed no voids in silicon field plates and gates. In addition, good electrical characteristics was demonstrated with the optimized process.

Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. The main method for reducing the trench width is to design large trench angle. However large trench angle for better characteristics causes some challenges. And process window always becomes narrow to get excellent characteristic. For quality control of trench angle, we found that the wafer warpage was related to the trench angle at two process steps. We confirmed these mechanisms by simulation and experiment. Furthermore, we examined which process step was appropriate for monitoring the trench angle by wafer warpage. Finally, we acquired four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation.

Field-Plate (FP) MOSFET structure has field-plate and thick oxide inside each trench. Due to the field-plate effect, it can improve tradeoff between low drift layer resistance and high breakdown voltage. In this structure, silicon wafer warpage is larger than that of conventional structure. It causes various problems in production, for example an error in vacuum adsorption or wafer transportation at manufacturing tools. In order to control the wafer warpage in manufacturing process, it is necessary to understand the wafer warpage peculiar to the FP-MOSFET comprehensively. The wafer warpage of the FP-MOSFET is different in X-/Y-directions because of influence of the stripe trench pattern extending in X-direction. We predict the warpage change in a newly designed FP-MOSFET by TCAD simulation, and study the reason of the warpage peculiar to the FP-MOSFET. Particularly, we explain six significant process steps, in which the warpage is greatly changed. Moreover, three process control techniques to reduce the wafer warpage are stated. This study enabled us to control the wafer warpage in process integration for the FP-MOSFET.

Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. Trench width is relevant to trench angle. However large trench angle for better characteristics causes the variation of the dielectric breakdown voltage on the oxide film that separating the gate and source. Therefore, process window becomes always narrow to get excellent characteristic. For quality control of trench angle, we find that wafer the warpage is relevant to the trench angle. We confirmed the dependence by simulation and experiment. Furthermore, we acquire four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation.

Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. We performed process optimization of FP-MOSFETs with sequential phosphorus-doped silicon. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. In addition, inserting 800°C annealing before 1000°C annealing contributes no voids in silicon field plates.

Silicon power MOSFETs have been used for a wide variety of electronic devices in many application fields. In order to obtain high breakdown voltage and low on-resistance, trench field-plate (FP) MOSFETs have been continuously developed in recent years. It is necessary to design deep trench and thick field-plate oxide for higher breakdown voltage FP-MOSFETs [1]–[6]. In state-of-the-art FP-MOSFETs, as shown in Fig. 1, high cell density design has been developed for the purpose of getting low on-resistance. Fundamentally, it needs to shrink cell pitch, which consists of trench width and mesa width. Forming vertical trench is one method to realize narrow cell pitch. Voids are, however, generated in source field-plate polysilicon or gate poly-silicon in general [7]. If voids are gathered widely at the bottom of the source field-plate polysilicon (Fig. 1(a)), the effect of field-plate such as high breakdown voltage and good device characteristics cannot be obtained properly. Furthermore, if voids are formed at the bottom edge of the gate poly-silicon (Fig. 1(b)), effective gate bottom edge is underlapped with p-base. Thus, it is difficult to form the channel inversion layer at gate oxide interface. As a result, the on-resistance becomes increased. Therefore, suppressing void generation is one of the most significant process controls for trench FP-MOSFETs.

We report a new N/PFET Gate Patterning Boundary Proximity layout dependent effect in high-k dielectric/Metal Gate (HK/MG) MOSFETs which causes anomalous threshold voltage (V t ) modulation for the first time. We investigated the mechanism by using special test structures and process optimizations to suppress this layout dependency. Finally, we achieved the best over all process optimization which makes it possible to suppress layout dependency without degrading FET performance/yield/reliability.

In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT∼2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k∼2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.

We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), Lg = 35 nm high performance TaCx/HfSiON devices is achieved.

We have designed the lithography process for 32nm node logic devices under th e 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um 2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects. Keywords : single exposure, low-k1 lithography, 32nm-node, dose-focus budget INTRODUCTION Immersion lithography is needed to shrink the design rule. The appearance of immersion lithography extends the optical lithography. In 45nm node, over 1.0NA tool is useful for pulling up the k 1 factor. The k 1 factors of 45nm node are about 0.37 for local metal level and 0.44 for contact hole level. For 32nm node, over 1.3NA tool becomes to be available. According to the design rule shrink trend, the minimum pitch of local metal and hole is about 100nm. The k1 factor is 0.34 for critical levels. Then, we have to overcome the issues of the low-k

For the fist time, low supply voltage SRAM operation with stress-enhanced dopant segregated Schottky (DSS) source/drain transistors is demonstrated. At constant SRAM cell current of 40 muA, we achieve two orders of magnitude lower bit-line leakage than conventional technologies at Vdd=0.7 V, while in case of constant bit-line leakage of 10 nA, supply voltage is successfully reduced down by 0.1 V. DSS technology is promising for low voltage SRAM operation for 32 nm node and beyond.

The effects of inversion-layer capacitance and stress-induced mobility at short channel region (Lg =35 nm) on (100) and (110) pFETs are investigated. 64 % mobility enhancement at Eeff = 1.1 MV/cm and 0.15 nm thinner inversion-layer capacitance at Eox = 4.5 MV/cm are obtained for (110) embedded SiGe (eSiGe) pFETs, compared to (100) eSiGe pFETs. Calculated results suggest that (110) eSiGe pFETs will gain additional 63% higher mobility with 1 GPa uniaxial stress by controlling surface roughness scattering at SiO2/Si(110) interface.

Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V.

Silicide compatible process flows for dual-gate CMOS with shallow extensions formed after activation annealing and Co SALICIDE (SEFAS) are proposed and adopted for 80 nm physical gate length CMOS. They show good DC and AC performances while keeping high reliability because of successful shallow extension formation. High f/sub T/ values of 80 GHz for NMOS and 47 GHz for PMOS are achieved.

A 0.15 /spl mu/m CMOS technology integrating W/WNx/polysilicon gate electrodes and Ti silicided source/drain diffusions is presented in this paper. Gate electrodes with sheet resistance as low as 1.6 /spl Omega//sq. and Ti silicided source/drain diffusions of 3.6 /spl Omega//sq. are realized. As a result, both the gate RC delay and parasitic source/drain resistance are minimized and high circuit performance is achieved.

A new technology of cobalt SALICIDE (Self-ALIgned siliCIDE) process using cobalt-titanium alloy has been developed for sub-quarter micron devices. Extremely flat and epitaxial CoSi/sub 2/ films are successfully grown on a (100) Si substrate. Improved SALICIDE process is not influenced by native oxide on a Si surface. This technology will be very useful for realizing deep sub-quarter micron devices.

This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced logic process is compatible with 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 /spl mu/m/sup 2/ 6 transistor SRAM. Two kinds of high V/sub dd/ devices can be prepared by the triple gate oxide process. Moreover, for mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors are introduced into Cu and low-k interconnects.

Demonstrates an optimum design of low leakage 85nm gate CMOSFET (I/sub off//spl les/3pA//spl mu/m) for 100nm technology node. Gate dielectric module has been optimized to achieve low gate leakage, low flicker noise and sufficiently high driving current. Deep source/drain design is strongly restricted from controlling junction leakage current when integration of trench DRAM cell is considered. Especially, for nMOSFET, deep junction is formed only by using phosphorus to suppress defect creation. Short channel immunity and suppression of gate depletion are achieved simultaneously by introducing gate pre-doping technique. In addition, channel and halo profiles are optimized to reduce band-to-band tunneling (BTBT) current. As a result, we have achieved excellent performance of /spl Sigma/CV/I(=CV/I/sub dn/+CV/I/sub dp/)=10.8psec with I/sub off/=3pA//spl mu/m at V/sub dd/ of 1.2V.

In this paper, mixed signal LSI operating at a single drain voltage of 1.5 V is shown. Integration of high performance logic MOSFET with analog MOSFET is achieved by optimizing channel structures. Very high performance and competitive drive currents of 830 /spl mu/A//spl mu/m for nMOS and 390 /spl mu/A//spl mu/m for pMOS at 1 nA//spl mu/m off currents are achieved by careful halo optimization in logic MOSFET. In analog part, indium channel is applied for satisfying low threshold voltage specification which comes from dynamic range viewpoint. This indium channel MOSFET shows superior analog performance. By applying indium retrograde channel, high DC gain values which are approximately ten times lager than the uniform boron channel case are achieved in addition to wide bandwidth and good Vth matching. It is found that well anneal temperature which is carried out soon after channel ion implantation is very sensitive to analog performance in indium retrograde channel. This optimization is significant for DC gain and matching.

Silicide technology using cobalt-titanium alloy has been developed for sub-quarter micron devices. Extremely flat and epitaxial CoSi2 films are successfully grown on a (100) Si substrate. Improved SALICIDE process is not influenced by native oxide on a Si surface. This technology will be very useful in deep sub-quarter micron devices.

High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance G m, conductance G ds, G m/I d, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., I on–I off, I off–V tsat, DIBL, C jswg) and reliability (HCI) have also shown the comparability of HPA devices over control.

Improved Ti self-aligned silicide (SALICIDE) technology for 0.1 µm complimentary metal-oxide-semiconductor (CMOS) using high dose pre-amorphization implantation (PAI) is developed. High dose PAI with As and Ge promotes the growth rate of silicidation on polycrystalline silicon gate even when its length is reduced to 0.1 µm. Thus it achieves low sheet resistivity at narrow lines. In addition, the advantage of Ge over As as PAI species is confirmed. Ge PAI does not affect the parasitic resistance increase of p channel metal-oxide-semiconductor field effect transistor (pMOSFET) or junction leakage characteristics because of its electrical neutrality and high solubility in silicon.