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The occam programming language, based on the CSP formal algebra and tied to a specific hardware platform (transputers), offered a structured way to organize concurrency. The CT library [1], developed at University of Twente, inspired by occam is a kernel library implementing occam primitives in modern programming languages and for general purpose microprocessors. In this paper, a practical implementation of the CT library is explained and some aspects are compared to similar occam-like library developed at the University of Kent. The design of the CT-library internals is then revisited and proposed changes are implemented in the C++ version of the library.

This paper presents a method to automatically generate a Control Data Flow Graph (CDFG) from C/C++ source code. This CDFG is used to automate the programming of an FPFA, a flexible, energy efficient reconfigurable device, introduced in the Chameleon project.

We present a tool for composition of component specifications. The tool uses UML diagrams to model the composition. A fixed component specification is a contract between some roles communicating via interfaces. A contract has a specific underlying model that we present. Composition of contracts is a contract that extends contracts of composites, but does not change them. To guarantee this feature we built some rules of the composition into our tool. Our tool is an ADD-IN of the Rational Rose that allows to produce consistent interface suite specifications in form of UML diagrams and documentation and to reuse such specifications in system design by composition.

Currently, computer-based control systems are still being implemented using the same techniques as 10 years ago. The purpose of this project is the development of a design framework, consisting of tools and libraries, which allows the designer to build high reliable heterogeneous real-time embedded systems in a very short time at a fraction of the present day costs. The ultimate focus of current research is on transformation control laws to efficient concurrent algorithms, with concerns about important non-functional real-time control systems demands, such as fault-tolerance, safety, reliability, etc. The approach is based on software implementation of CSP process algebra, in a modern way (pure objectoriented design in Java). Furthermore, it is intended that the tool will support the desirable system-engineering stepwise refinement design approach, relying on past research achievements ¿ the mechatronics design trajectory based on the building-blocks approach, covering all complex (mechatronics) engineering phases: physical system modeling, control law design, embedded control system implementation and real-life realization. Therefore, we expect that this project will result in an adequate tool, with results applicable in a wide range of target hardware platforms, based on common (off-theshelf) distributed heterogeneous (cheap) processing units.

This paper proposes a home network which integrates both real-time and non-real-time capabilities for one coherent, distributed architecture. Such a network is not yet available. Our network will support inexpensive, small appliances as well as more expensive, large appliances. The network is based on a new type of real-time token protocol that uses scheduling to achieve optimal token-routing through the network. Depending on the scheduling algorithm, bandwidth utilisations of 100 percent are possible. Token management, to prevent token-loss or multiple tokens, is essential to support a dynamic, plug-and-play configuration. Small appliances, like sensors, would contain low-cost, embedded processors with limited computing power, which can handle lightweight network protocols. All other operations can be delegated to other appliances that have sufficient resources. This provides a basis for transparency, as it separates controlling and controlled object. Our network will support this. We will show the proposed architecture of such a network and present experiences with and preliminary research of our design.

The design for a new type of non-volatile mass storage memory is discussed. This new design, based on scanning probe techniques, combines the low volume and power consumption of the FlashRAM, with the high capacity of the hard disk. The small form factor of the device makes it an excellent candidate for mass storage in handheld embedded systems. Its hierarchical architecture allows us to make a trade-off between data-rate, access time and power consumption. The power consumption scales linearly with the desired data-rate, and is expected to be lower than what can be achieved with competing technologies.

We present a jukebox scheduler for real-time data. The scheduler is part of a hierarchical real-time file system to be used over a network. A jukebox is a large tertiary storage device whose removable media (e.g. cd-rom, dvd-rom) are loaded and unloaded from one or more drives by a robot. The problem with tertiary storage is that media exchange times are high and the number of drives is limited. This makes scheduling tertiary storage complicated. The storage media switching time in a jukebox is in the order of tens of seconds. Therefore multiplexing between two files stored in different media is many orders of magnitude slower than doing the same in secondary storage. The goal of the scheduler is to schedule the use of the jukebox devices (arm and drives) in such a way that the system can guarantee the deadlines while minimizing the response time. The problem is similar to that of scheduling multiple processors with the additional difficulty of having to deal with the high switching times and the use of a shared resource (the arm). Finding an optimal schedule is an NP-hard problem. We provide a near-optimal polynomial solution by using heuristics to prune the tree of solutions. The scheduling time is in average less than 100 ms. The incoming requests are scheduled on-line.

A major problem in performance evaluation of real-life industrial systems is the enormous number of states generated by the system's model during the simulation process. An example is in a Parallel Object-Oriented Specification Language (POOSL) model, which can be interpreted as a discrete-time Markov chain enabling the evaluation of long-run average performance metrics. In general this Markov chains is huge, making performance simulation expensive since all performance estimations must be updated in each state. In this paper, we introduce a method for performance evaluation based on Markov chain theory, which aims at the reduction of the original Markov chain into a smaller chain. We prove that the reduction yields another Markov chain and it preserves several important properties. We further give a method to effectively construct the reduced chain. The reduction method yields an efficient way to estimate performance metrics during model simulation, since in general it requires estimations to be updated only in a relatively small part of the state space.

Real-time, performance and reliability aspects are of vital importance in the entire system design trajectory. Therefore, modelling techniques are needed that cover quantitative system aspects. This paper presents MoDeST, a modelling language that allows us to specify soft real-time constraints (i.e., stochastic timing) as well as hard real-time constraints. MoDeST combines conventional programming constructs – such as iteration, alternatives, atomic statements, and exception handling – with means to describe complex systems in a compositional manner. The language is influenced by popular and user-friendly specification languages, and deals with compositionality in a light-weight process-algebra style. In summary, MoDeST (i) covers a very broad spectrum of modelling concepts, (ii) possesses a rigid, process-algebra style semantics, and (iii) yet provides modern and flexible specification constructs.

In an in-home digital network it may be expected that several data (audio, video) streams run simultaneously over a shared communication device, e.g. a bus. The burstiness a data stream can have can be reduced by buffering data at the sending and receiving node connected to the bus, thereby allowing a lower bus bandwidth allocation for the stream. In this paper we present an algorithm that determines how much bandwidth and buffer space should be allocated to each stream. We model the problem as a linear program and apply a Dantzig-Wolfe decomposition to decompose the multiple-stream problem into several single-stream problems. For these single-stream problems we present sketches of efficient algorithms to solve them.

We present a specification tool for comonent specification that uses UML diagrams as an illustration of the specification. A component is specified as a set of roles communicating via interfaces, named an interface suite. Our tool is based on a specification model for interface suites and it is realized as a specific extension of the Rational Rose UML-based tool.

Before implementing a system with hardware and software components, performance modelling is often used for evaluating design alternatives. The formal modelling language Parallel Object-Oriented Specification Language (POOSL) has proven to be very useful for analysing performance metrics of design alternatives for real-life industrial systems. Based on its mathematically defined semantics, POOSL enables to analytically compute performance metrics by analysing the Markov chain that is implicitly defined by a POOSL model. Models of real-life industrial systems are however often too complex to be analysed exhaustively. Performance evaluation is therefore based on simulation, enabling the estimation of performance metrics. However, simulation results only have a proper meaning if their accuracy is known. In general, longer simulation yields more accurate results. To analyse the accuracy of simulation results and automatically terminate the simulation after accurate results have been obtained, confidence intervals can be used. Based on the properties of the Markov chains implicitly defined by POOSL models, this paper presents a technique of regenerative cycles for analysing the accuracy of long-run sample average estimation. Furthermore, an algebra of confidence intervals is defined to enable accuracy analysis of long-run time averages as well as long-run sample and time variances. Finally, library classes are introduced for POOSL, which ease accuracy analysis for the mentioned performance metric types.

The process-algebraic language µcrl is used to analyze an existing distributed system for lifting trucks. Four errors were found in the original design. We propose solutions for these problems and show by means of model-checking that the modified system meets the requirements.

A trend in automation is the increasing connectivity of devices and applications in order to provide new types of functionality. To combine functionality, it is necessary that devices can communicate with each other. In recent years, we have seen the emergence of a special type of software, called middleware, that aims at inter-application communication. Middleware typically achieves this by providing application interfaces that make communication transparent to the application processes. In this paper we present ActiveLink: a middleware solution for embedded systems that provides cross-platform communication between applications, is lightweight, easily portable, and supports many communication protocols. ActiveLink has been developed by CMG, supported with research from the Eindhoven University of Technology. We illustrate features that distinguish ActiveLink from mainstream middleware by listing some of the main requirements for deployment in the area of embedded systems and explain how these requirements influenced the architecture and design of ActiveLink.

In this paper we address the problem of scheduling non-manifest data dependant periodic loops for high throughput DSP-applications based on a streaming data model. In contrast to manifest loops, non-manifest data dependent loops are loops where the number of iterations needed in order to perform a calculation is data dependant and hence not known at compile time. For the case of manifest loops, static scheduling techniques have been devised which produce near optimal schedules [1]. Due to the lack of exact run-time execution knowledge of non-manifest loops, these static scheduling techniques are not suitable for tackling scheduling problems of DSP-algorithms with non-manifest loops embedded in them. We consider the case where (a) apriori knowledge of the data distribution, and (b) worst case execution time of the non-manifest loop are known and a constraint on the total execution time has been given. Under these conditions dynamic schedules of the non-manifest data dependant loops within the DSP-algorithm are possible. We show how to construct hardware which dynamically schedules these non-manifest loops. The sliding window execution, which is the execution of a non-manifest loop when the data streams through it, of the constructed hardware will guarantee real time performance for the worst case situation. This is the situation when each non-manifest loop requires its maximum number of iterations.

Within PROGRESS project WebES we look at connecting embedded systems to the Internet. Part of the project concerns issues related to mobility and mobile communication. We look at small footprint implementations of Corba specifically destined for mobile terminals and compare several different implementations in that respect. In addition, we look at the issue of modelling systems containing wireless connections.

Connecting other devices than workstations to the Internet is becoming commonplace now. We give a taxonomy of such devices based on the integration of this connection with the functionality of the device. Then we propose a generic architecture for web-connected devices based on Internet standards. We present the Device Monitoring and Control Protocol (DMCP) that we derived from the prototypes we have build. As a running example to illustrate DMCP, we used a physiotherapy device.

The assessment of quality attributes of software-intensive systems is a challenging issue. This paper describes a method aimed at quantitative evaluation of certain quality attributes that are important design parameters for embedded systems; timeliness, performance and memory consumption. The following principles are important starting points for building a formal model for evaluating quality attributes: (1) Dependability constraints are specified in an end-to-end fashion; (2) Components are attributed with resource demands; (3) Specification of component interaction is separated from specification of component behavior. Furthermore, the method is aimed to be applicable in practice. Therefore we investigate combining of widely used software modeling notations with existing formal methods. In particular, the proposed approach combines Message Sequence Charts and Timed Automata. We illustrate the approach with an example.

Many applications can be structured as a set of processes or threads that communicate via channels. These threads can be executed on various platforms (e.g. general purpose CPU, DSP, FPGA, etc). In our research we apply channels as a basic communication mechanism between threads in a reconfigurable system. The research involves providing system level functions to describe the setup of communicating threads, which may now either run timeshared on a general CPU or in dynamically-setup special purpose logic that runs on reconfigurable hardware. The use of channels and threads running in both software and hardware, will be made transparent for the application level programmers by the system level functions. By first describing the threads and how they are connected and then letting the operating system decide on 'geographical' placement of the threads and buffers, multiprogramming will be supported and programs will be able to run on different setups of hardware (i.e. different amount of CPUs or available programmable logic). This is an ongoing work, the paper is a collection of thoughts, which lead to a first setup of rudimentary support functions in the operating system.

Experiments with strong localized electron cyclotron heating (ECH) in the RTP tokamak show that electron heat transport is governed by alternating layers of good and bad thermal conduction. For central deposition hot T-e filaments are observed inside the q = 1 radius. Moving the ECH resonance from the centre to the edge of the plasma results in discrete steps of the central electron temperature. The transitions occur when the minimum q value crosses q = 1, 2, 5/2 or 3, and correspond to the loss of a transport barrier situated close to the rational q value. Close to the transitions a new type of sawtooth activity is observed, characterized by the formation of sharp off-axis maxima on the T, profile, which collapse abruptly. The formation of the off-axis maxima is attributed to heat deposition precisely 'on top of' a transport barrier.