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There is a life after breast cancer. The prerequisite is early detection. Breast cancer is curable when detected early, tiny, and has not spread – regular screening aids in early detection. Clinical Thermography and artificial intelligence are potentially a good fit for early breast cancer screening. This survey paper presents a systematic review of artificial intelligence-based breast cancer screening using thermal infrared cameras. Initially, we will present the qualitative analysis of the existing literature regarding the trend and distribution. This review manuscript will then explore the literature about infrared thermal image acquisition and storage techniques. We will then highlight various segmentation techniques used for processing infrared thermal images. This paper presents the experimental results of the traditional image processing and deep learning-based segmentation techniques available in the literature using infrared breast thermal images. We then summarize the works that have used artificial intelligence to segment and classify infrared thermal images. The existing literature shows opportunities to explore the area of explainable artificial intelligence (AI). Explainable AI will make clinical Thermography into assistive technology for the medical community. [ABSTRACT FROM AUTHOR]

Transactional memory (TM) is being viewed by researchers as a suitable mechanism to perform shared-memory synchronization on upcoming many-core systems. This paper provides an introductory material on TM, followed by a background of important historical work on synchronization leading to current TM research. The paper reviews recent pure hardware and hardware-software TM design proposals, and finally brings out a list of interesting open problems in this field. [ABSTRACT FROM AUTHOR]

Error concealment in video communication is becoming increasingly important because of the growing interest in video delivery over unreliable channels such as wireless networks and the Internet. A subclass of this error concealment in video communication is known as motion vector recovery (MVR). MVR techniques try to retrieve the lost motion information in the compressed video streams based on the available information in the locality (both spatial and temporal) of the lost data. The activities and practice in the area of MVRbased error concealment during the last two decades has been mainly elaborated here. A performance comparison of the prominent MVR techniques has also been presented. [ABSTRACT FROM AUTHOR]

The H.264 encoded video is highly sensitive to loss of motion vectors during transmission. Several statistical techniques are proposed for recovering such lost motion vectors. These use only the motion vectors that belong to the macroblocks that are horizontally or vertically adjacent to the lost macroblock, to recover the latter. Intuitively this is one of the main reasons behind why these techniques yield inferior solutions in scenarios where there is a non-linear motion. This paper proposes B-Spline based statistical techniques that comprehensively address the motion vector recovery problem in the presence of different types of motions that include slow, fast/sudden, continuous and non-linear movements. Testing the proposed algorithms with different benchmark video sequences shows an average improvement of up to 2 dB in the Peak Signal to Noise Ratio of some of the recovered videos, over existing techniques. A 2 dB improvement in PSNR is very significant from an application point of view. [ABSTRACT FROM AUTHOR]

In a highly dynamic semiconductor manufacturing technology, the migration to the next process technology node tries to create a smaller-faster-cheaper chip. To achieve this, the integrated circuit (IC) designs are becoming more complex and new manufacturing materials/processes are introduced. Additionally, demands for sustainable yield and shorter time to volume production have to be met as they govern the profitability of the semiconductor industry. As a result, rapid yield improvement techniques are crucial to overcome huge yield losses. Any yield improvement technique typically involves detecting the yield loss (testing) and identifying its root cause (diagnosis). This paper presents a survey of the existing research work reported in the literature for test and diagnostics of nanometer chips and presents interesting open issues. [ABSTRACT FROM AUTHOR]

This study proposes a novel motion vector recovery (MVR) algorithm for the H.264 video coding standard, which takes into account the change in the motion vectors (MVs) in different directions. Existing algorithms for MVR are confined to use the horizontal or vertical directions to recover the lost MVs. However, in the presence of non-linear movements or a fast/sudden motion of any object in a scene of the given input video, the MVs recovered by these algorithms turn out to be inaccurate. The proposed directional interpolation-based technique can interpolate the MVs in any direction based on the tendency of motion around the lost macro block, thus making it suitable to handle non-linear or fast motions. Testing the proposed technique with different benchmark video sequences shows an average improvement 1–2 dB in the peak signal-to-noise ratio of the recovered video over existing techniques. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, the design of a parallel architecture for on-line face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed. The WMPCA methodology, proposed by us earlier, is based on the assumption that the rates of variation of the different regions of a face are different due to variations in expression and illumination. Given a database of sample faces for training and a query face for recognizing, the WMPCA methodology involves division of the face into horizontal regions. Each of these regions are analyzed independently by computing the eigenfeatures and comparing the same with the corresponding eigenfeatures of the faces stored in the sample database to calculate the corresponding error. The final decision of the face recognizer is based on the weighted sum of the errors computed from each of the regions. These weights are calculated based on the extent to which the various samples of the subject are spread in the eigenspace. The WMPCA methodology has a better recognition rate compared to the modular PCA approach developed by Rajkiran and Vijayan [Rajkiran, G., Vijayan, K., 2004. An improved face recognition technique based on modular PCA approach. Pattern Recognition Letters, 25(4), 429–436]. The methodology also has a wide scope for parallelism. We present an architecture that exploits this parallelism and implement the same as a system-on-programmable-chip on an ALTERA based field programmable gate array (FPGA) platform. The implementation has achieved a processing speed of about 26 frames per second at an operating frequency of 33.33MHz. [Copyright &y& Elsevier]

Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes novel pseudo-online built-in self-test based techniques for detecting and locating multiple faults in lookup tables (LUTs), interconnects and dedicated clock lines of field programmable gate arrays (FPGAs). The techniques use the partial reconfiguration capabilities of modern FPGAs. The methods proposed in this paper find extensive applications in safety critical systems like space probes, which comprises of several subcircuits mapped onto the FPGA and employs online checkers to report misbehaviour of any of these subcircuits. When an online checker reports misbehaviour of one such subcircuit, the methods proposed in this paper attempt to detect and locate the faults, if any, within the faulty subcircuit without shutting down the other subcircuits. The methods presented in the paper preserve the routing structure of the configured application in-place. Experimentally, it is shown that the proposed methods provide good fault-coverage in identifying faults in LUTs, interconnects and dedicated clock lines. [Copyright &y& Elsevier]