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11 results on '"Kalivaraprasad, B."'

1. A Comparative Study of Power Optimization Using Leakage Reduction Techniques

Author

Aylapogu, Pramod Kumar, Jayalakshmi, A., Praveena, Hirald Dwaraka, Kalivaraprasad, B., Akan, Ozgur, Editorial Board Member, Bellavista, Paolo, Editorial Board Member, Cao, Jiannong, Editorial Board Member, Coulson, Geoffrey, Editorial Board Member, Dressler, Falko, Editorial Board Member, Ferrari, Domenico, Editorial Board Member, Gerla, Mario, Editorial Board Member, Kobayashi, Hisashi, Editorial Board Member, Palazzo, Sergio, Editorial Board Member, Sahni, Sartaj, Editorial Board Member, Shen, Xuemin, Editorial Board Member, Stan, Mircea, Editorial Board Member, Jia, Xiaohua, Editorial Board Member, Zomaya, Albert Y., Editorial Board Member, Nandan Mohanty, Sachi, editor, Garcia Diaz, Vicente, editor, and Satish Kumar, G. A. E., editor

Published
2023
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2. A Novel Voltage Level-Up Shifter Design for Power Efficient Methods Using Dual Current Mirror Technique

Author

PramodKumar, Aylapogu, Kalivaraprasad, B., Prasad, M. V. D., Jayalakshmi, A., Ravichand, S., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Tomar, Anuradha, editor, Malik, Hasmat, editor, Kumar, Pramod, editor, and Iqbal, Atif, editor

Published
2022
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3. An Area and Delay-Efficient Approximate Hybrid Adder for VLSI Circuit Designs

Author

Kalivaraprasad, B., Prasad, M. V. D., Raju Kumar Singh, Ch., Ravichand, S., Pramod Kumar, A., Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Tomar, Anuradha, editor, Malik, Hasmat, editor, Kumar, Pramod, editor, and Iqbal, Atif, editor

Published
2022
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4. Comparative Analysis of Watermarking Methods on CFRP Sample Thermal Images

Author

Kalivaraprasad, B., Prasad, M. V. D., Rajesh Babu, K., Shameem, Syed, Mohan, S., Vani, Vasudevan, Kacprzyk, Janusz, Series Editor, Gomide, Fernando, Advisory Editor, Kaynak, Okyay, Advisory Editor, Liu, Derong, Advisory Editor, Pedrycz, Witold, Advisory Editor, Polycarpou, Marios M., Advisory Editor, Rudas, Imre J., Advisory Editor, Wang, Jun, Advisory Editor, Bhateja, Vikrant, editor, Satapathy, Suresh Chandra, editor, Travieso-Gonzalez, Carlos M., editor, and Flores-Fuentes, Wendy, editor

Published
2021
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6. Design and Modelling of Tunnel Field Effect Transistor- using TCAD Modeling

Author

Kalivaraprasad B, S. Ravi Chand, S. Koteswari, P. Madhu Sudhan Reddy, K. Sai Anurag, and K. Palanivel Rajan

Subjects
Human-Computer Interaction, Computer Networks and Communications, Electrical and Electronic Engineering, Software, Information Systems
Abstract

The purpose of this research was to suggest a junction-less strategy for a vertical Tunnel Field Effect Transistor, which would increase the device's efficiency. In this study, we examine the similarities and differences between a negative capacitor TFET and a vertically generated TFET with a source pocket and a heterostructure-based nanowire gate. And how the channel transit impacts the output qualities of a sub-100 nanometer sized device. The Silvaco TCAD (a commercially available tool) was used to simulate a tri-layer high-K dielectric made of hafnium zirconium oxide (HZO) and titanium dioxide (TiO2) materials as gate stacking to the V-TFET and GAA-NC-TFET structures, and the tunnelling and transport parameters were calibrated experimentally. A short bandgap material, GaSb, in the home region to enhance carrier tunnelling via the mentioned three source (GaSb)-channel (Si) heterojunction at varying biases were utilized. Motion, tube length, and saturating velocity are only few of the transport channel characteristics that are investigated. As a result of the building's vertical orientation, the electric field is enhanced, allowing for an ION current of up to 104 Am2. The most unexpected result of this device is that a high ION/IOFF may increase mobility and reduce saturation velocity, perhaps reducing the drain voltage at saturation. The proposed biosensor's sensitivity was multiplied by 108 when vertical and lateral tunnelling were used in tandem. We apply a variety of optimisation strategies to deal with this problem, despite the fact that quantum confinement reduces the effect of mobility variations on device performance. When biomolecules were positively charged, the drain current increased, and when they were negatively charged, the drain current decreased.

Published
2023

7. Design and Speed Analysis of Low Power Single and Double Edge Triggered Flip Flop with Pulse Signal Feed-Through Scheme

Author

R. Gomathi, S. Gopalakrishnan, S. Ravi Chand, S. Selvakumaran, J. Jeffin Gracewell, and Kalivaraprasad B.

Subjects
Electrical and Electronic Engineering, Engineering (miscellaneous)
Abstract

Flip flop is a fundamental electrical design component. Most electrical designs incorporate memory and their corresponding designs. The consumer electronics or end users need mobility and extended battery backup to enhance design performance. The focus on any parameter in the system is to maximize the performance of the design. Here the task is to reduce the energy use of flip flop. Due to the increased frequency clock delivered to the networks within the design, the edge or level triggered by a flip flop will contribute to power consumption. Due to the short circuit power consumption between ground and Vdd, the static design of the flip flop will increase power consumption. The flip flop is dynamically designed and implemented, leading to higher leakage power. Dynamic clock implementation helps for short-circuit power avoidance. It also provides greater download channel to the ground from output. The clocking system also demands more power. With the TSPC technology and output feedback, the suggested mechanic will increase the performance of the flip flop and establish the Pull-up network. The PMOS that contains the output node X value. The use of an additional NMOS transistor to draw the output value down to the ground, regardless of the input, so that the input runs on the discharge path that improves power, however the pulsed clock which has a smaller width than normal clock as well about 15% high.

Published
2022

10. Analysis of food recognition and calorie estimation using AI.

Author

Kalivaraprasad, B., Prasad, MVD, Vamsi, R., Tejasri, U., Santhoshi, M. NVVSLD, and PramodKumar, Aylapogu

Subjects
*FOOD chemistry, *CONVOLUTIONAL neural networks, *ARTIFICIAL neural networks, *ARTIFICIAL intelligence, *FOOD habits, *CALORIC content of foods, *CHILDHOOD obesity
Abstract

Nowadays, regular intake of nutritious foods is essential for maintaining a healthy eating routine and avoiding obesity in the human body.. In this paper, a novel framework dependent on AI that naturally performs exact grouping of food pictures and gauges food credits. In the preparation section of the model system, it proposes a profound learning model that includes a convolutional neural organization that orders food into explicit classifications. The principle reason for the proposed technique is to improve the exactness of the pre-preparing model. The paper plans a model framework dependent on the customer worker model. The customer sends a picture location solicitation and cycles it on the worker side. Support Vector Machine (SVM), Artificial Neural Network (ANN), and Convolution Neural Network (CNN) are the three classifiers that have been modified to analyze the framework's enhanced precision. Exploring various avenues about a variety of food groups, each with a large number of images, using Artificial Intelligence (AI) to achieve higher grouping precision. [ABSTRACT FROM AUTHOR]

Published
2021
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