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Due to a sharp decline in resources, Schizothorax waltoni Regan and Percocypris retrodorslis have been listed as wildlife under second-class protection in China. Under culture conditions, the early development and allometric growth patterns of S. waltoni and P. retrodorslis were researched from the hatching stage to 60 DPHs (days post-hatching), and a sampling of ten to fifteen larvae was made every day, followed by measurements with Axio Vision 4.8 software (Carl Zeiss AG, Jena, Germany). Morphological indicators included the anal fin length, the body depth, the body depth at the anus level, the caudal fin length, the dorsal fin length, the eye diameter, the head length, the head depth, the pectoral fin length, the tail length, the trunk length, the snout length, the total length, and the ventral fin length. Based on the morphology development of S. waltoni Regan and P. retrodorslis, four periods of larval growth were identified: pre-flexion larvae at 0–14 DPHs and 0–16 DPHs; flexion larvae at 14–23 DPHs and 16–26 DPHs, post-flexion larvae at 23–50 DPHs and 26–52 DPHs, and the juvenile stage. In newly hatched larvae, most organs and body parts were not differentiated, and they successively developed within 26 DPHs. The depletion of the yolk sac was observed at 23 DPHs and 25 DPHs. Allometric growth mainly occurs in the head and tail regions, indicating that body parts related to feeding and swimming behaviors were more important than the other parts. In addition, the growth pattern shows that the development of organs gives priority to the functions of gill respiration, sensation, exogenous feeding, and swimming. The inflection points of body part growth patterns only appeared before 40 DAH, so future studies should concentrate focus on developing the best feeding from the first feeding to 40 DAH. These outcomes were discussed with regard to the ontogeny of the functional morphology in relation to ecology and aquaculture. It is expected that this research can provide valuable perspectives in species conservation.

An effectively perceptual preprocessing filter method will reduce the sequence’s perceptually insignificant details, which can help to alleviate the video coding’s pressure and benefit the coding results. In this paper, a perceptual rate distortion optimization based preprocessing filter algorithm is presented to achieve better video compression performance. The proposed algorithm employs an adaptively temporal filter with the rate SSIM (Structure Similarity Index Metric) based optimization constraint to produces optimal filter parameters. The evaluation results confirm that the proposed video filter algorithm has achieved reliable rate-visual quality improvements with -4.35% and -2.96% SSIM based BD-Rate performance gain on JM18.3 and HM16.9, respectively. Additionally, the subjective quality comparison results show that our algorithm has reduced significant bits with negligible visual difference for both the experiments on JM18.3 and HM16.9.

Integer motion estimation (IME), which acts as a key component in video encoder, is to remove temporal redundancies by searching the best integer motion vectors for dynamic partition blocks in a macro-block (MB). Huge memory bandwidth requirements and unbearable computational resource demanding are two key bottlenecks in IME engine design, especially for large search window (SW) cases. In this paper, a three-level pipelined VLSI architecture design is proposed, where efficiently integrates the reference data sharing search (RDSS) into multi-resolution motion estimation algorithm (MMEA). First, a hardware-friendly MMEA algorithm is mapped into three-level pipelined architecture with neglected coding quality loss. Second, sub-sampled RDSS coupled with Level C + are adopted to reduce on-chip memory and bandwidth at the coarsest and middle level. Data sharing between IME and fractional motion estimation (FME) is achieved by loading only a local predictive SW at the finest level. Finally, the three levels are parallelized and pipelined to guarantee the gradual refinement of MMEA and the hardware utilization. Experimental results show that the proposed architecture can reach a good balance among complexity, on-chip memory, bandwidth, and the data flow regularity. Only 320 processing elements (PE) within 550 cycles are required for IME search, where the SW is set to 256 × 256. Our architecture can achieve 1080P@30 fps real-time processing at the working frequency of 134.6 MHz, with 135 K gates and 8.93 KB on-chip memory.

We introduce a perceptual video quality driven video encoding solution for optimized adaptive streaming. By using multiple bitrate/resolution encoding like MPEG-DASH, video streaming services can deliver the best video stream to a client, under the conditions of the client's available bandwidth and viewing device capability. However, conventional fixed encoding recipes (i.e., resolution-bitrate pairs) suffer from many problems, such as improper resolution selection and stream redundancy. To avoid these problems, we propose a novel video coding method, which generates multiple representations with constant JustNoticeable Difference (JND) interval. For this purpose, we developed a JND scale estimator using Support Vector Regression (SVR), and designed a pre-encoder which outputs an encoding recipe with constant JND interval in an adaptive manner to input video.

The aim of this paper is to investigate the existence of exponential attractors for lattice reaction-diffusion systems in weighted spaces $l_{\sigma}^{2}$ and for partly dissipative lattice reaction-diffusion systems in weighted spaces $l_{\mu}^{2}\times l_{\mu}^{2}$ , respectively. In contrast to the previous work by Abdallah in J. Math. Anal. Appl. 339, 217---224 (2008) and Commun. Pure Appl. Anal. 8, 803---818 (2009), we get the existence of exponential attractors for lattice dynamical systems in the weak topology spaces.

The emerging high efficiency video coding standard (HEVC) achieves significantly better coding efficiency than all existing video coding standards. The quad tree structured coding unit (CU) is adopted in HEVC to improve the compression efficiency, but this causes a very high computational complexity because it exhausts all the combinations of the prediction unit (PU) and transform unit (TU) in every CU attempt. In order to alleviate the computational burden in HEVC intra coding, a fast CU depth decision algorithm is proposed in this paper. The CU texture complexity and the correlation between the current CU and neighbouring CUs are adaptively taken into consideration for the decision of the CU split and the CU depth search range. Experimental results show that the proposed scheme provides 39.3% encoder time savings on average compared to the default encoding scheme in HM-RExt-13.0 with only 0.6% BDBR penalty in coding performance.

Recently, high-efficiency video coding becomes more and more demanded as the explosive requirements of network bandwidth and storage space for surveillance video applications. In this paper, we propose a background modeling scheme based on high efficiency motion classification. Firstly, pixels at each location are classified into three motion states, namely the static, the gentle motion and the severe motion states, according to the motion vectors of the corresponding current block and neighboring blocks. Then based on the classification and pixel differential value, the segmentation is performed for the co-located pixels in the training frames, and the mean pixel value of each segment can then be calculated. Finally, the background modeling frame can be obtained by an optimized weighted average of the segmented mean pixel values. Experimental results show that our proposed scheme achieves an average PSNR gain of 0.65dB than the AVS surveillance baseline video encoder, and it gets the best performance among several high efficiency background modeling methods in fast motion and large foreground sequences.

It has been widely demonstrated that integrating efficient perceptual measures into traditional video coding framework can improve subjective coding performance significantly. In this paper, we propose a novel block-level JND just-noticeable-distortion model, which has not only adjusted pixel-level JND thresholds with more block characteristics, but also integrated them into a block-level model. And the model has been applied for adaptive perceptual quantization for video coding. Experimental results show that our model can save bit rates up to 24.5% on average with negligible degradation of the perceptual quality.

This paper presents a highly efficient external memory interface architecture to improve memory bandwidth utilization for AVS HD video encoder. Both burst and bank interleaved SDRAM accesses are intelligently adopted in the memory interface design. Our proposed architecture is composed of an address mapping layer and an arbitration layer. In the address mapping layer, according to the data request pattern and quantity, the clients in the encoder are divided into four groups which are assigned to different banks of the SDRAM. In each group, efficient address mapping schemes are proposed to minimize inner client overhead. In the arbitration layer, a straightforward group-based interleaved arbitration scheme is proposed to minimize inter client overhead. Experimental results show that the data access overhead cycles of our proposed interface design are reduced significantly and the bandwidth utilization is improved by up to 10% compared to the tile-linear address mapping scheme.

This paper presents a new video encoder architecture for H.264 and AVS, which adopts a novel macroblock (MB) encoding order. As a replacement of Level C+ zigzag coding order, the so-called Level C+ slash scan coding order with NOP insertion is used as MB scheduling to remove MB-level data dependency of the pipeline so that the left MB's coded results such as motion vector (MV) and reconstructed pixels can be obtained early in motion estimation (ME) stages. As a result, by sharing the reconstruction (REC) loop, sequential intra prediction (INTRA) can be split into multiple pipeline stages to explore more block-level parallelization and rate distortion optimization (RDO) based mode decision is apt to implement. The exact MV predictors (MVP) obtained in motion estimation can not only improve coding performance but also make pre-skip ME algorithm able to be applied into this architecture for low power applications. Since the proposed scheme is attributed to Level C+ data reuse, the bandwidth is decreased greatly. A real-time high-definition (HD) 1080P AVS encoder implementation on FPGA verification board with search range [−128, 128]×[−96, 96] and two reference frames at an operating frequency of 160 MHz validates the efficiency of proposed architecture.