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In this paper, we analyze the occurrence of jitter due to random and deterministic disturbances in nonautonomous current-mode logic circuits. First, we present an analytical model that explains the transformation of noise into jitter as a linear time-variant process, with its time-domain impulse response function and a frequency-domain system function. The model is then used to analyze jitter in two different circuits, with different sources of noise. In the first example, we use the model to predict jitter due to device noise in a frequency divider, and identify devices that are the main contributors to the jitter. In the second example, we examine jitter of a buffer with deterministic ground noise. Jitter predictions are compared to the results obtained through exhaustive simulation. According to the comparison, the method predicts jitter with an error of up to 3.4%.

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 /spl mu/m CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary.

A new voltage-mode CMOS multiple-valued logic (MVL) memory circuit has been realized in a standard 2 μm p-well polysilicon-gate CMOS technology. This circuit requantizes MVL voltages during a setup clock mode and latches the input value during the hold clock mode. Using a 5 V supply and logical voltage increments of 1 -67 V, a quaternary memory circuit with a worst-case total setup and hold time of about 7 ns, and a best single-level transition total setup and hold lime of about 1 ns has been realized.

A continuous-time NTSC-to-color-difference decoder has been fabricated in a 2-/spl mu/m CMOS process. The 9-mm/sup 2/ decoder includes the chrominance IF filter, automatic gain control, timing recovery, 90/spl deg/ phase shift, demodulators, hue and saturation controls. The 90/spl deg/ phase-shift circuit is based on peak detection and is used for tuning the chrominance IF filter and demodulation of the R-Y signal. The total power dissipation is 45 mW on /spl plusmn/2.5-V supplies. All circuits are fully differential. This allows the timing-recovery outputs to achieve a differential phase of 0.1/spl deg/ over a horizontal-line interval. For a standard NTSC 1 V/sub p-p/ color-bar input, the R-Y and B-Y outputs exhibit maximum phase and gain errors of 1.1/spl deg/ and 1.5/spl deg/, respectively.

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >

A new latch circuit for bi-directional multiple-valued logic (MVL) current signals has been realized in a standard 2-microri poly-silicon gate CMOS process. The circuit accepts and quantizes a bi-directional input current during the SETUP clock phase and latches the quantized input during the HOLD clock phase. Using logical current increments of only l0μA, the bi-directional current-mode MVL latch set-up and hold time has been determined to total approximately 45 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 45 ns at these low current levels.

The quaternary full adder accepts two quaternary inputs and a binary CARRY input and develops a two-quaternary-digit output word that is the base-four sum of the inputs. A current-mode CMOS circuit is presented that implements the quaternary threshold logic full adder function more area efficiently, with fewer current comparators and decoders (and hence transistors), than previously reported. It has been realized in standard polysilicon-gate CMOS technology.

The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 mu m CMOS technology, this 13.3 mm*13.3 mm chip is designed to handle images as large as 1024*1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy. >

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance. >

A unified discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) architecture is used in the design of a proposed single-chip VLSI implementation of this function. An 8-point by 1 organization of the DCT/IDCT is chosen to allow easy implementation of the 8 × 8 format under consideration for recommendation by the International Consultative Committee for Telephone and Telegraph (CCJTT) for 384 K-bit CODECs. Fast DCT and IDCT algorithms are merged into a single hardware architecture that is programmable with a single DCT/IDCT selection switch. To accomplish real-time 10 MHz video data processing, the basic system clock brings data in and sends data out each 100 ns. Eight pixels are loaded for simultaneous processing every 800 ns and the module of each pipeline stage processes these eight elements simultaneously. Algorithm simulations and experimental performance of integrated test sub-circuit prototypes indicate that this proposed new DCT/IDCT chip would be capable of the real-time proces...

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32/spl times/32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm /spl times/ 8.2 mm.

A new VLSI chip performs both image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MIIz. Realized in 1 pm CMOS technology, this 13.3mm x 13.3mm chip is designed to handle images as large as 1024 x 1024 12-bit pixels. Loadable coefficients allow this chip to be used with a variety of computed-tomography scanners for image reconstruction, including fan-beam reconstruction. The bit lengths in the fixed-point architecture assure 12-bit reconstruction accuracy.

A high-voltage (HV) SOI CMOS VLSI chip has been demonstrated to transport droplets on programmable paths across its coated surface. This HV exciter for a fluidic lab-on-a-chip system creates dielectrophoretic forces that move and help inject droplets. Electrode excitation voltage and frequency are variable: at 100V, f/sub ELECmax/ = 200Hz. Data communication rate is variable up to 250kHz. This 10,377/spl mu/m-by-8210/spl mu/m demonstration chip has a 32/spl times/32 array of nominally 100V electrode drivers dissipating 1.87W max.

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over fifty percent savings in the total number of signal variables required to implement the parallel counter results. With the circuits we describe here, fifty percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters.

Correlation techniques are widely used in analog and digital signal processing; e.g. in optiman receiver design. In this paper, a new digital output correlator circuit design is proposed. The correlation results are presented as a binary count of the number of bits in agreement between 31-bit reference and input sequences. Correlation results could be presented at data rates up to about 50MHz. The proposed new circuit could be implemented in a high speed bipolar transistor technology as a monolithic large-scale-integrated circuit with a power dissipation of about .5 watts. A novel pipelined 31-bit digital summing circuit will be presented that employs new multivalued, multithresholded latching and counting circuits in the formation of its binary-coded output. Comparisons with an all-binary digital correlator circuit are made.

A computer-aided design (CAD) tool is being developed to assist in analog and mixed-signal electronic system design through the use of design optimization. This CAD tool uses technology- and implementation-independent high-level behavioral models. These computationally efficient behavioral models are expressions of the relationships among terminal variables of common electronic, MEMS, photonic, electro-mechanical, and other signal processing functions. These behavioral models include limiting behaviors in the DC, time domain, and frequency domain. These models are not based upon specific semiconductor devices, circuit configurations, or fabrication technologies. Simulations using these computationally efficient behavioral models allow designers of mixed-signal systems to evaluate alternative architectures in less time, at lower computational cost than possible with traditional semiconductor device-level simulation. With an efficient means of evaluating the performance of a mixed-signal system architecture available, we use design optimization to adjust the figures of merit of the behavioral models to achieve the desired terminal characteristics of the overall system architecture.

A new voltage-mode comparator circuit for use in CMOS multiple-valued logic circuits is introduced. Existing comparator circuits for this application use static current or clocking and thus consume static power or clocking power. In order to reduce these power requirements, we have examined static circuit designs that eliminate DC current paths when the inputs and outputs are at logical values. Elimination of DC current paths requires increased circuit complexity, layout area, and signal delay. This paper proposes comparator circuits that use static logic circuits and thus require no static current and no static (DC) power. HSPICE simulations of these circuits using model parameter values for a 0.35-/spl mu/m n-well CMOS technology and a 3.3-volt power supply show that each of these comparator circuits consumes static power on the order of nW. Simulations with the model parameter values for the thick-oxide (5-volt) option of the 0.35-/spl mu/m technology and for a 1.2-/spl mu/m (5-volt) CMOS technology are also presented. These power levels are consistent with those of standard binary CMOS logic circuits in the same technologies.

A high-speed Radon transform computer (RTC) has been designed and simulated that operates on the principles of the parallel projection pipeline engine (PPPE) processor suggested by J.L.C. Sanz, et al. (1988). The computer consists of an array of identical processing elements with fast communication links to each of its neighbors and uses forward- and back-projection formulas tests linear interpolation. Simulation and experimental timing tests have been performed on both a systolic array of 64 transputer processors and on arrays of commercial DSP (digital signal processor) chips. A custom VLSI implementation is currently under design which is expected to perform forward and inverse transforms of 512 by 512 images at or near video rates. >

Adaptive lattice noise cancelling algorithms have features that make them appear attractive for the realization of real-time adaptive noise cancellers with single-chip digital signal processors. Two popular adaptive lattice noise cancelling algorithms have been evaluated for this application: the stochastic gradient lattice and least-squares lattice algorithms. For the purpose of comparison, the stochastic gradient transversal algorithm is also evaluated. Their performances under a variety of signal and noise excitations are summarized and compared in terms of operating rates, convergence rates, and misadjustments. >

A CMOS current-mode quaternary threshold logic latch circuit is proposed. This circuit accepts and requantizes quaternary logical currents during a setup clock mode and latches the input value during the hold clock mode. Using logical current increments of 10 mu A, the quaternary latch has been simulated to have a worst-case, three-logical-level transition, total setup and hold time of about 40 ns, and a single-level transition total setup and hold time of about 10 ns. >

CMOS quaternary threshold logic circuits are used in the design of the instruction memory and arithmetic sections of a proposed single-chip implementation of a unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture. The chip is projected to be capable of real-time processing of 10-MHz video signals. The unified DCT/IDCT architecture is described, and the use of quaternary logic circuits is discussed. A 17.5% area savings has been achieved. >

A unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture suitable for VLSI implementation is presented. A single VLSI NMOS chip design and layout for realizing this architecture is described. Algorithm simulations and experimental performance of integrated test subcircuits indicate that this chip would be capable of real-time processing of 10-MHz video signals. It is considered that circuits of this type could be very useful in real-time image data compression. >

Image reconstruction from projection data is very computationally intensive. A novel IC architecture is presented which can be used in a pipeline of identical ICs to reconstruct images from parallel- and fan-beam scanner configurations. The accuracy and the finite word-length effects of fan-beam reconstruction are considered. Software simulations of the architecture designed in a 1 mu m CMOS technology show that a maximum clock speed of 40 MHz is possible under nominal operating conditions. >

A current-mode CMOS algorithmic analog-to-quaternary data converter circuit has been realized in a standard polysilicon-gate CMOS technology. This circuit accepts an analog current input and uses current comparators and pass gates to develop a set of quaternary, base-four, output currents. A single type of converter cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits. The current-mode CMOS algorithmic analog-to-quaternary data converter circuit is presented, and its experimental and simulated performances are described. >

Several of the current-mode CMOS multiple-valued-logic (MVL) circuits that the author has studied over the past decade are reviewed. These circuits include a simple current threshold comparator, MVL encoders and decoders, quaternary threshold logic full adders (QFAs), MVL latches, latched QFA circuits, and analog-to-quaternary converter circuits. >

Multiple valued logic (MVL) has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. These performance improvements are achieved by designers who identify signal processing functions that can benefit from the design tradeoffs possible with MVL. Since advocates of MVL are accustomed to incorporating the possible tradeoffs of MVL techniques into specific VLSI design applications, these MVL designers may be able to take advantage of new energy saving circuit design techniques that may have tradeoffs that complement those of MVL. Low-energy (adiabatic) logic circuits have been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional dc power supply, these logic circuits use "ac" power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. It is possible to integrate all power switches and control circuitry on the chip with the low-energy logic. This results in better system efficiency and simpler power distribution. In this paper, concepts of adiabatic circuit design and the use of a high-frequency resonant power clock generator for adiabatic circuits will be summarized and then their possible application to low-energy, adiabatic multiple valued logic is discussed.

Behavioral simulation of complex, inherently highly nonlinear mixed-signal systems is often the only effective way to evaluate possible system performance before fabrication and characterization of the hardware system. Transistor-level, SPICE, simulations of these systems are often practically impossible because of the enormous computational time required due to the many interactions of all the nonlinearities and the widely separated system time constants. New behavioral models for useful electronic functions have been developed as straightforward mathematical descriptions that can be evaluated by general purpose mathematical programs and system simulators. The models are targeted for MATLAB and use standard MATLAB expressions and linked C and FORTRAN codes. An example PLL behavioral model is presented and evaluated by comparing simulated performance to actual experimental integrated circuit performance. >

A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2- mu m polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using logical current increments of only 10 mu A, the bidirectional current-mode MVL latch's setup and hold time has been determined to total approximately 44 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 50 ns at these low current levels. >

A special-purpose VLSI array is proposed for performing the computations of the Jacobian, inverse Jacobian, direct kinematics, and numerical integration for the implementation of a joint-space position and velocity command generator for a real-time robot. This integrated approach enhances computational efficiency by reducing the duplicate calculations of these functions and maximizing the parallel/pipelining processing. The array is connected in a systolic manner to form a 6*7 array using 42 basic processing elements (PEs); 6 'circular' PEs, 30 'square' PEs, and 6 'triangular' PEs. A 'square' PE test chip has been designed and fabricated. The test results for this chip show that the array should be able to operate at a step time of 150 ns. For a six-link manipulator with rotary joints, it takes 156 steps, i.e., 23.4 mu s, to complete all the computations in one sampling period. >

A unified Radon-transform/back-projection IC that is capable of performing the forward Radon transform and back-projection computations in a multiprocessor array architecture is being designed in a CMOS technology. The architecture of the IC and related design considerations are presented. This chip would make possible high-quality image reconstruction to 12-b resolution at video rates. >

Experimental performances of new low-power, reliable start-up CMOS RC and crystal oscillators are presented. The oscillators use a modified Fabre-Normand translinear current conveyor for realization of their negative impedance converter. Measurements show reliable oscillation start-up for power supply voltages that range from 1.5 V to 5 V with current consumption from 100 nA to 1.2 mA, respectively. Oscillation frequencies up to 55 MHz have been observed in circuits fabricated in a modest 2 /spl mu/m CMOS technology.

A simple new continuous-time CMOS comparator circuit with supply-to-supply input common-mode range is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit requires an area of 416 /spl mu/m/spl times/221 /spl mu/m in a MOSIS 2-micron CMOS technology. It operates at 3 V and requires between 0.5 and 1.3 mA. Delays of between 54 and 282 ns have been measured.

A new analog subsystem design approach is presented that can be used to improve the accuracy, reliability, yield, and testability of analog and mixed-signal CMOS ICs. The proposed scheme is a generally applicable design approach that combines hybrid redundancy, direct subcircuit parameter adjustment, and on-chip analog function verification. Improvements are realized in a system-transparent fashion through function block commutation. The cost is a moderate die area increase. Although applicable to any moderately complex analog function, the example analog function used to illustrate this new design approach presented here is the op amp. Experimental data demonstrate the capabilities of this new design approach.

A new adiabatic CMOS logic that operates from a single-phase power-clock is presented. A simple and efficient power-clock generator is integrated with the logic to generate the required AC power-clock supply waveform. Circuit performance is evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings comparable to other adiabatic logic families that require multiphase power-clocks.

In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.

Voltage-mode CMOS multiple valued logic memory circuits have been realized in a standard 2-micron p-well polysilicon-gate CMOS technology. These circuits requantize multiple-valued logical voltages during a SETUP clock mode and latch the input value during the HOLD clock mode. Using a 5 volt supply and logical voltage increments of 1.67 volts, two similar quaternary memory circuits have worst-case total SETUP and HOLD times of about 5.7 ns and 7 ns; and best single-level transition total SETUP and HOLD times of about 0.9 ns and 1 ns.

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed.

Experimental results for new low-power, reliable start-up CMOS RC oscillators are presented. The oscillators use a modified Fabre-Normand translinear current conveyor. Measurements show reliable oscillation start-up for power supply voltages that range from 1.5 V to 5 V with current consumption from 100 nA to 1.2 mA, respectively. Oscillation frequencies up to 55 MHz have been observed in circuits fabricated in a modest 2 /spl mu/m CMOS technology.

A new voltage-mode quaternary CMOS static latch circuit is presented that is built around a binary standard CMOS logic clocked RS latch circuit. Only devices available in a standard digital CMOS fabrication technology-enhancement-mode NMOS and PMOS transistors with single threshold voltage values-are used. No depletion-mode devices or special transistor threshold voltages are required. Its operation is experimentally verified. Typical and worst-case on-chip setup and hold times are simulated to be approximately 2.8 ns and 6.8 ns, respectively.

The Radon transform and its inverse, commonly used for computed tomography (CT), are computationally burdensome for single processor computers. Since projection-based computations are easily executed in parallel, multiprocessor architectures have been proposed for high-speed operation. In this paper, we describe an architecture for a high-speed (30 MHz raster-scan image data rate), high accuracy (12-bits per pixel) computed-tomography system for use in non-destructive inspection system. This architecture reconstructs images from fan- or parallel-beam data using either single-pass or iterative reconstruction techniques. Our architecture uses a number of identical processor modules in a pipeline. Each processor module consists of memory for data storage, a commercially available digital signal processing (DSP) chip for filtering, and our custom IC which performs 450 million mathematical operations per second (MOPS). This architecture can reconstruct CT images as large as 1024 X 1024 pixels from a variety of image reconstruction algorithms. The details of the implementation and performance of our expandable architecture are discussed.

The amount of data generated by computed tomography (CT) scanners is enormous, making the image reconstruction operation slow, especially for 3-D and limited-data scans requiring iterative algorithms. The inverse Radon transform, commonly used for CT image reconstructions from projections, and the forward Radon transform are computationally burdensome for single-processor computer architectures. Fortunately, the forward Radon transform and the back projection operation (involved in the inverse Radon transform) are easily calculated using a parallel pipelined processor array. Using this array the processing time for the Radon transform and the back projection can be reduced dramatically. This paper describes a unified, pipelined architecture for an integrated circuit that computes both the forward Radon transform and the back projection operation at a 10 MHz data rate in a pipelined processor array. The trade-offs between computational complexity and reconstruction error of different interpolation schemes are presented along with an evaluation of the architecture's noise characteristics due to finite word lengths. The fully pipelined architecture is designed to reconstruct 1024 pixel by 1024 pixel images using up to 1024 projections over 180 degrees. The chip contains three pipelined data-paths, each five stages long, and uses a single multiplier.© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A new voltage-mode CMOS quaternary threshold logic latch circuit that has been realised in a standard 2 mu m p-well polysilicon-gate CMOS technology is presented. This circuit requantises quaternary logical voltages during a SETUP clock mode and latches the input value during the HOLD clock mode. Using a 5 V supply and logical voltage increments of 1.67 V, the quaternary latch has a worst-case total SETUP and HOLD time of approximately 5.7 ns. and best single-level transition total SETUP and HOLD time of approximately 0.9 ns. >

A current-mode CMOS circuit that realises the latched quaternary threshold logic full adder function has been realised in standard polysilicon-gate CMOS technology. In its FOLLOW mode, the quaternary full adder accepts two quaternary inputs and a binary CARRY input and develops a two-quaternary-digit output word that is the base-four sum of the inputs. In the HOLD mode, these output states are held by a eight-valued current-mode latch subcircuit. A current-mode CMOS latched quaternary threshold logic full adder circuit is presented and experimental performance described.

Adaptive lattice noise cancelling algorithms have features that make them appear attractive for the realisation of realtime adaptive noise cancellers with single chip digital signal processors. Two popular adaptive lattice noise cancelling algorithms have been evaluated for this application. Considered are stochastic gradient lattice and least squares lattice algorithms. For the purpose of comparison, the stochastic gradient transversal algorithm is also evaluated. Their performances under a variety of signal and noise excitations are summarised and compared in terms of operating rates and misadjustments.

Frequency-doubling circuits for analogue and digital systems are described. Typical modern frequency doubling circuit implementations are first reviewed. An extremely simple digital frequency-doubling circuit technique is then presented and subsequently applied to both sinusoidal and square waveforms. The performance of this simple circuit and others are compared.

High speed second-order digital filters with maximum input-Sampling frequencies of 2·86 MHz can be realized with a single multiplier-accumulator IC using the filter architecture presented. Extensions to N'th order digital filters are also presented

A real-time adaptive line enhancer hardware system has been implemented for noise cancellation in a nuclear fusion instrumentation project. The noise cancellation circuitry, realized with a standard digital signal processor (DSP) chip, uses a direct form adaptive filter and adapts using the least-mean-squares (LMS) algorithm. The noise cancellation circuitry adapts the noise filter weights to the line noise prior to an experiment. Upon initiation of the experiment, the adaption is stopped for the duration of the experiment. Experimental data with noise cancelling may be recorded during the experiment. After the experiment, noise filter weights may be read out to be included with the experimental record for possible later evaluation. The use of these hardware systems could significantly reduce the presently enormous requirements for off-line signal processing to extract plasma information. In this paper, real-time capabilities of the line enhancer circuitry for noise cancellation are demonstrated for simpl...

Subnanosecond switching circuits employing a proposed new non-uniformly doped junction field effect transistor (NUDJFET) are simulated and compared to simulated and published experimental test results of similar configurations employing uniformly doped devices. The non-uniform channel doping of the NUDJFET octs to lower its saturation voltage, thus allowing a given circuit configuration to operate at a lower power supply voltage with very little speed degradation and hence a reduced speed-power product. Several important switching circuit configurations are simulated and their speed and power performances compared and evaluated.