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Two a-Si thin-film transistors (TFTs) demultiplexer circuits, resistive load (RL) and complementary-like logic (CLL), are proposed and compared with the conventional pass transistor logic (PTL) demultiplexer circuit. Analytical and experimental results indicate that the proposed RL and CLL demultiplexers outperform the PTL circuit by providing larger output voltage swings (OVSs), faster dynamic responses, and less OVS sensitivities to the device instability. The pulse-bias stress experiments, simulating the normal condition of operation, are conducted both on individual a-Si TFTs and a-Si TFT demultiplexer circuits, and the variations in device/circuit electrical characteristics are measured during 12 h. The measurement results indicate that the OVS degradation of proposed circuits can be limited to 7 mV/h, suggesting a long circuit lifetime.

This paper presents a four-stage CMOS distributed amplifier (DA) design implemented in standard 0.18 mum CMOS technology. The proposed design eliminates the need for transmission line capacitors and, consequently, uses significantly smaller spiral inductors compared with the previous designs. Using the minimum size inductor, the bandwidth of the amplifiers is extended, and the quality factors of the on-chip inductor are improved. Proposed DA occupies the smallest die area (0.3mum*0.8mum) amongst the DAs reported with the same performance. A unity gain bandwidth of 10 GHz and a gain of 15 dB are measured. DC power dissipation is 56 mW