1. Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier
- Author
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Kazuyoshi Takagi, K. Taketomi, Masamitsu Tanaka, Nobuyuki Yoshikawa, Koji Obata, Naofumi Takagi, Yuki Yamanashi, H. Hara, Heejoung Park, Akira Fujimaki, and Shuichi Nagasawa
- Subjects
Floating point ,Computer science ,business.industry ,Clock rate ,Electrical engineering ,Integrated circuit ,Condensed Matter Physics ,Electronic, Optical and Magnetic Materials ,law.invention ,Microprocessor ,CMOS ,law ,Low-power electronics ,Multiplier (economics) ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,business ,Electronic circuit - Abstract
We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2 Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.
- Published
- 2009
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