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Dielectric breakdown in 2D insulating films for future logic device technology is not well understood yet, in contrast to the extensive insight we have in the breakdown of bulk dielectric films, such as HfO2 and SiO2. In this letter, we investigate the stochastic nature of breakdown (BD) in hexagonal boron nitride (h-BN) films using ramp voltage stress and examine the BD trends as a function of stress polarity, area, and temperature. We present evidence that points to a non-Weibull distribution for h-BN BD and use the multi-scale physics-based simulations to extract the energetics of the defects that are precursors to BD, which happens to be boron vacancies.

Singapore University of Technology and Design (SUTD) in Singapore was set up in January 2010 to tackle global challenges of the 21st century and beyond. To truly address human-centric issues and problems, a design-focused curriculum using an outside-in approach was adopted in formulating its undergraduate degree programmes in engineering and architecture. This has led to the formation of degree programmes focusing on products, services, systems and built environment which the world needs. To break down the silo mentality and promote multidisciplinary education, SUTD adopts a very forward-looking approach in its academic structure in which majors are offered by four multidisciplinary pillars, supported by two clusters. The absence of conventional colleges, faculties, departments and even divisions encourages seamless and boundaryless collaboration in education and research across all pillars and clusters. With a strong focus on Big-Design (i.e., Big-D) throughout and across courses, semesters and domain areas, undergraduate students are well equipped with skills and attitudes through 20 to 35 team-based Big-D projects during their undergraduate education to provide learning experiences beyond book knowledge, preparing them well with various soft skills such as creativity, critical thinking, teamwork and others before embarking on their career in industry. Coupled with small group-cum-active or peer-to-peer learning in a dedicated cohort classroom environment, the SUTD undergraduate programme further encourages students by having them collaborate with each other across pillars to foster teamwork and a collaborative spirit in formulating and sharing solutions beyond the team. Besides being recognized by the "Global State-of-the-Art in Engineering Education" report commissioned by the MIT School of Engineering [1] as the top of the emerging leader in engineering education recently, the response from industry for the first 5 batches of undergraduates has been very positive.

In replacing the conventional SiO2 gate dielectric with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the different properties of the new bulk oxide and the interfacial layers at the substrate and gate electrode interface as well. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in resistive random access memory (RRAM). In this study, we explore the stochastic nature of hard breakdown recovery in HfO2, taking advantage of ramped voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more intense after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring the resistance change trends with temperature.

Polysilicon (poly-Si) grain size control is a critical issue with scaling of MOS transistors in integrated-circuit design, more so in embedded nonvolatile memory (NVM) technology. This paper investigates an approach to suppress poly-Si grain growth under a necessary additional thermal budget for 40-nm embedded NVM technology. Our studies reveal that carbon implant can suppress poly-Si grain size growth and that the implant dose rather than its energy plays a key role in controlling the grain size. Physical analysis using advanced planar transmission electron microscopy technique shows a reduction in the poly-Si grain size with an increasing carbon implant dose. The application of the carbon implant technique to sub-40 nm embedded NVM technology can therefore help to reduce SRAM ${V} _{{MIN}}$ -related failures significantly. In this paper, we present a complete process reliability case study to incorporate carbon implant as an effective solution for suppressing poly-Si grain growth, thereby eliminating the side effects of an additional thermal budget in advanced embedded NVM.

This paper presents a comprehensive stochastic simulation approach combining resistor network embedded metropolis Monte Carlo method and the finite-element method for modeling FinFET oxide degradation. The geometrical impact of the 3-D structure is linked with the stochastic model, and the simulation method can evaluate the degradation behavior of FinFET structures accounting for geometrical variations and multiphysics coupling effects. The leakage current, electric field, current density, and temperature distribution are simulated and show good agreement with electrical stress test data. The simulation results also indicate the need for a bimodal clustering model to best describe FinFET degradation and dielectric breakdown lifetime statistics. The proposed simulation methodology is generic enough to be fine-tuned for reliability modeling of other logic and nonvolatile memory devices in the future.

This study investigates the resistive switching characteristics and underlying mechanism in 2D layered hexagonal boron nitride (h-BN) dielectric films using conductive atomic force microscopy. A combination of bipolar and threshold resistive switching is observed consistently on multi-layer h-BN/Cu stacks in the low power regime with current compliance (I comp ) of less than 100 nA. Standard random telegraph noise signatures were observed in the low resistance state (LRS), similar to the trends in oxygen vacancy-based RRAM devices. While h-BN appears to be a good candidate in terms of switching performance and endurance, it performs poorly in terms of retention lifetime due to the self-recovery of LRS state (similar to recovery of soft breakdown in oxide-based dielectrics) that is consistently observed at all locations without requiring any change in the voltage polarity for I comp ~1–100 nA.

The time-dependent dielectric breakdown phenomenon (TDDB) has been investigated in a series of nominally identical MgO based magnetic tunnel junctions (MTJs) by pulsed voltage endurance test. Results from the pulsed endurance test reveal that the breakdown voltage is dependent on the polarity of the applied voltage. MTJs with “UP” current stress ( I up ) (flowing from reference layer (RL) to free layer (FL)) show higher endurance than that of MTJs with “DOWN” current stress ( I down ). We also found that bipolar stressing could result in reduced cumulative stress time before failure as compared to unipolar stressing. This could be explained by increased charge trapping/detrapping effects during bipolar stressing. The asymmetric breakdown behavior for different polarity was further supported by the different field acceleration slopes observed in the mean time to failure (MTTF) – voltage bias trend line. Symmetric pulse scheme breakdown measurements were also carried out at different temperatures ranging from 25–85 °C. The time-dependent clustering model is applied here to best describe the breakdown statistics in view of the non-uniformity in percolation breakdown due to thickness variations (interface roughness) and other process-induced damages to the ultra-thin MgO barrier layer.

In a comprehensive analytical study of dielectric breakdown (BD) of ultra-thin MgO in 28 nm embedded MRAM (eMRAM) test chips, it was observed that breakdown in MgO is polarity dependent, and that device lifetime is reduced for bipolar (AC) stress. Furthermore, it was found that the breakdown trend substantially deviates from the Poisson area scaling law; this deviation can be attributed to self-heating in larger area devices. Further investigation of BD also reveals that self-heating effects are predominantly observed at lower frequencies; percolation paths exhibit fast transient (thermal runaway) temperatures; and that BD statistics are poorly represented by the standard Weibull model.

Resistive switching in high-κ (HK) dielectric based metal-insulator-metal (MIM) devices occurs locally and is accompanied by dynamic changes in the structural and electrical properties of the HK dielectric. In polycrystalline HfO 2 HK dielectric based MIM devices, grain boundaries (GBs) play a significant role in the formation of a percolation path for the resistive switching as the GB regions contain a large number of defects and favor the formation of conductive/low resistive paths. In this work, we present a multi-physics based combined Kinetic Monte Carlo-Finite element model (KMC-FEM) 3D percolation framework to simulate the resistive switching (high resistive state (HRS) to low resistive state (LRS)) process in TiN/HfO 2 (5 nm)/Pt MIM stacks. The KMC-FEM model describes the effect of GBs on the formation of conductive path during the HRS to LRS resistive switching. In addition, this model is used to find the statistical distribution of conductive filament/path formation in amorphous and polycrystalline HfO 2 dielectrics. Conductive atomic force microscopy and transmission electron microscopy observations on the characteristics of the HfO 2 dielectrics at the nanometer scale complement the simulation results. The results clearly show that the HRS to LRS resistive switching occurs preferably at the GB regions in polycrystalline HfO 2 and at random locations in amorphous HfO 2 -based MIM stacks.

Most studies on resistance switching have been carried out at the device level with the standard electrical characterization setup, which allows for effective automated reliability test and extensive characterization of the lifetime of an RRAM device. However, it is equally important to be able to probe the switching phenomenon at the nanoscale so as to improve insight on the bias-dependent kinetic behavior of the filament during multiple reversible breakdown and recovery cycles. This study aims to do just that by probing HfO2 blanket films (~ 4 nm) with a W bottom electrode using an ultra-sharp Pt-wire conductive AFM (CAFM) tip with an areal resolution of ~10–20 nm at ambient conditions. The use of the CAFM allows for a more reliable assessment of single filament evolution behavior as possible multiple filamentation events (common at the device level) are rare for such small probing areas. The role of oxygen vacancy induced filaments is studied here by using low compliance setting and moderate voltage levels, ensuring operation in the sub-quantum conductance regime. Our results show good repeatable switching trends and also provide insight on the quantum conductance phenomenon in oxygen vacancy based filaments. The read disturb trends in switching are investigated for the high resistance state (HRS) and the impact of tip-induced mechanical stresses on forming lifetime is also presented, which could serve as a motivator for further studies on non-volatile memory (NVM) reliability for flexible electronics devices and system on chip (SoC) applications.

Resistive random access memory (RRAM) devices with a nickel top electrode form controllable metal nanofilaments and have robust resistive switching performance. We investigate the Ni/HfO 2 /SiO x /n + Si RRAM structure, which forms a Ni-rich defect in the silicon underneath the Ni nanofilament in the dielectric layers after a SET process. The formation of these defects may affect the retention of the devices, so we applied a detailed Finite Element Method and Kinetic Monte Carlo approach to simulate the Ni-rich defect evolution under different compliance current settings. We confirm that the chemical composition of the defects is metallic NiSi 2 , and that their size is determined by the compliance current. These simulation results are supported by in-situ STM-like experiments inside a transmission electron microscope (TEM). NiSi 2 defects are shaped as truncated square pyramids, and we show that this is due to the low activation energy of Ni migration along the (111) crystal plane of Si. Our results demonstrate that electromigration is the main driving force for Ni migration initially, after which thermal migration and especially stress migration become the dominant mechanism. This work gives a fascinating example of an as-grown metal–insulator–semiconductor (MIS) system that can be controllably converted to a metal–insulator–metal (MIM) configuration for down-scaled RRAM operation.

The interface between III-V and metal-oxide-semiconductor materials plays a central role in the operation of high-speed electronic devices, such as transistors and light-emitting diodes. The high-speed property gives the light-emitting diodes a high response speed and low dark current, and they are widely used in communications, infrared remote sensing, optical detection, and other fields. The rational design of high-performance devices requires a detailed understanding of the electronic structure at this interface; however, this understanding remains a challenge, given the complex nature of surface interactions and the dynamic relationship between the morphology evolution and electronic structures. Herein, in situ transmission electron microscopy is used to probe and manipulate the structural and electrical properties of ZrO2 films on Al2 O3 and InGaAs substrate at the atomic scale. Interfacial defects resulting from the spillover of the oxygen-atom conduction-band wavefunctions are resolved. This study unearths the fundamental defect-driven interfacial electric structure of III-V semiconductor materials and paves the way to future high-speed and high-reliability devices.

The time-dependent dielectric breakdown (TDDB) phenomenon has been investigated in a series of nominally identical dual-MgO CoFeB magnetic tunnel junctions (MTJs) by bipolar pulsed voltage endurance tests using 28 nm embedded MRAM (eMRAM) test chip. From the bipolar pulsed endurance tests on different size MTJ devices, we show that the dielectric breakdown for MgO deviates significantly from the Poisson area scaling law due to self-heating in larger area devices. The lifetime of the devices was found to be longer for stressing with shorter pulse widths for the same overall cumulative stress duration, which could be attributed to the self-heating effects that typically take about a few microseconds to reach the saturation temperature. We prove that self-heating effects play a more dominant role than extrinsic etch damage effects in determining the lifetime of STTRAM devices.

In this study, we investigate the physical mechanism of soft and hard dielectric breakdown using conductive atomic force microscope (CAFM) as a nanoscale spectroscopy tool on blanket hexagonal boron nitride (h-BN) films with thickness of ∼ 4 nm grown on Cu substrate. The soft breakdown regime involves vacancies/defects (boron and/or nitrogen) rich percolation path formation while the hard breakdown regime shows nano-pore formation that involves removal of h-BN layers and formation of a metallic contact due to CAFM tip adhesion with the Cu substrate. Reduction of Weibull slope for successive soft breakdown events due to multiple ramp voltage tests at each location confirms the validity of the percolation model. We observe a concavity in the breakdown voltage distribution that can be explained by the thickness variations in h-BN layers. The clustering model is shown to be good candidate to describe the breakdown voltage distributions.

In this study, we present physical and statistical evidence to highlight the similarities and differences in the kinetics of the dielectric breakdown mechanism in FinFET devices, in comparison to their planar analogues. From a physical perspective, the mechanism of breakdown in FinFET devices still involves epitaxial silicon protrusion into the oxide during the progressive and hard breakdown stages, while the location of breakdown appears more confined to the bottom fin corners in almost all cases examined. From a statistical perspective, the Weibull distribution is no longer suitable for TDDB and residual time analysis. Instead, the clustering model becomes essential not only for wafer-level TDDB studies (due to process variations) but also for device-level studies, considering the field inhomogeneity and oxide thickness non-uniformity in the non-planar fin architecture. Bimodal distribution is observed in all stacks indicating the presence of two different failure mechanisms, possibly extrinsic and intrinsic. However, STEM-EELS and -EDX based examinations on several samples do not show any evidence for more than one physical process driving the degradation.

Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO 2 dielectric on the performance of underlying SiO x ( x ⩽ 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiO x IL beneath the GBs and thinner HfO 2 dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiO x IL.

Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO2-based high-κ dielectrics replacing SiO2 and metal gate replacing polysilicon and silicides, the physics of defect generation and breakdown of the oxide has changed significantly, although the mechanisms governing operation of the transistor remain essentially the same. Given the progression towards ultra-thin dielectric films with physical thickness ∼1–2 nm, the overall breakdown process has shifted from a single catastrophic hard breakdown (HBD) event to include various regimes such as soft breakdown (SBD) and progressive (post) breakdown (PBD) which in itself consists of a digital phase with random telegraph noise (RTN) fluctuations and stable average leakage current and an analog phase with gradual wear-out and lateral dilation of the percolation path resulting in a monotonic increase in leakage current. In order to better design and optimize the logic gate stack for enhancing its robustness and immunity to breakdown, it is essential to understand the driving forces and physical mechanisms behind the different phases of dielectric failure. This review is dedicated to the scientific understanding of the various regimes of breakdown in high-κ gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.

Physical mechanisms governing dielectric breakdown in planar devices have been well studied in the past [1, 2]. However, their extension to the study of non-planar FinFET structures has not received much attention, partly due to the assumption that the kinetics of failure would remain the same. We reveal in this study that this assumption is not true using advanced physical characterization techniques (TEM/EDX/EELS) as well as electrical-statistical tests and multiphysics simulations. The key findings of the study may be summarized as follows : (1) Progressive and hard breakdown in FinFETs is governed by silicon epitaxial defects originating from the channel; (2) The location of breakdown is almost always at the bottom corners of the fin; (3) Area scaling is invalid for fin width and height, but valid only for fin length and count; (4) Bimodal distributions are observed in TDDB due to dielectric micro structure variations; (5) Zero-bias drain breakdown events are localized in the central fins due to self-heating intensification and shift significantly towards the source when small drain bias is applied and (6) Clustering model is necessary to explain the stochastics of TDDB in FinFETs due to geometry induced nonuniform spatial electric field patterns.

Resistive Random Access Memory (RRAM) device is considered as a promising NVM device to replace flash memory device due to its simple design, small size and low operating conditions. The reliability of RRAM devices has been studied with respect to endurance, retention and variability for many years. However, the increasing demand of high performance and drastic down scaling trend make the reliability issues more challenging than before. In this work, a comprehensive study of hard breakdown (HBD) process in crossbar RRAM device was carried out via electrical, compositional and structural characterization methods. The results confirm that the HBD process was caused by Ta2O5 dielectric breakdown with intensive joule heating and melting process. The 3D structures of defects are well reconstructed. The percolation path was confirmed to be located at the edges of crossbar structure due to the low quality of peripheral materials and process variation. The presented work can offer a critical insight on preventing the HBD process in crossbar RRAM structure.

Graphical abstractDisplay Omitted The real-time observation of faster degradation at GB sites of HfO2 dielectric.C-AFM results show enhanced defect generation rate at the GB sites.Preferential breakdown of SiOx IL occurs below the degraded GB region.A breakdown sequence in polycrystalline HfO2/SiOx dielectric stacks was proposed. Grain boundaries (GBs) in polycrystalline high-? (HK) dielectric films affect the performance and reliability metrics of HK based advanced metal-oxide-semiconductor (MOS) devices. A full understanding of device reliability can only be had with the knowledge of the detrimental role of GB in degradation and breakdown (BD) of polycrystalline HK/interfacial layer (IL) dielectric stacks. In this work, we present a nanoscale resolution study on how the polycrystalline microstructure affects the degradation and BD at GB sites of polycrystalline HfO2 in HfO2/SiOx (x≤2) dielectric stacks using conductive-atomic force microscopy (C-AFM), supported by a statistical failure distribution model and device level simulations. Results clearly show an enhanced trap generation and faster degradation of polycrystalline HfO2 gate dielectrics at GB sites as compared to the bulk (grain) regions implying shorter time-dependent dielectric breakdown (TDDB) lifetime at the GB sites. The SiOx IL below the degraded GB experiences a BD event when an enhanced electric field across the SiOx IL reaches the critical BD field, eventually triggering the overall BD of the HfO2/SiOx dielectric stack.

The understanding of the switching mechanisms in resistive random access memory is of interest as one can use the fundamental mechanisms to better design the memory structure for enhancing both switching and reliability performance. Various analytical methods have been explored to better understand the wear-out and eventual failure mechanisms of RRAM stacks. This includes atomic-scale characterization methods like STM-/AFM-based techniques as well as enhanced TEM techniques and it derivatives like in-situ analysis while stressing the RRAM samples through electrical, optical and mechanical means at evaluated temperature. In this talk, we show that a direct observation of the mechanisms responsible for the switching phenomena in metal/oxide/semiconductor(MIS) RRAM stacks is possible by retrofitting a TEM sample holder with an electrical feed-through to a STM tip that applies an electrical bias to the MIS RRAM stack of interest. Real-time (or in-situ) switching information can be obtained for both SET and RESET cases. The developed techniques have been proven reliable in performing switching cycles many times while observing the switching phenomena under TEM analysis at nano-scale.

High resolution transmission electron microscope (HRTEM) is widely used in the study of various RRAM materials system. HRTEM can provide detailed cross sectional characterization of RRAM devices with compositional and structural information at the same time. Recently, scanning probe microscopy (SPM) techniques have also been explored to study oxygen vacancy based RRAM switching with detailed surface, electron energy and tomography information. This paper will introduce the recent RRAM switching studies enabled by advanced physical analysis techniques.

This paper for the first time successfully demonstrates a Logic-compatible, highly reliable, automotive-grade 16Mb flash macro with self- aligned, split-gate FG-based flash cell embedded into a 40nm Low Power CMOS with copper low-K interconnects. Key Features of the flash macro: Dual power supply with operation temperature from -40 to 150oC; Random Read access 10ns @ worst case condition; Low active and standby power; High raw endurance and data retention lifetime before using ECC. This technology provides large read current window which is compatible with both automotive MCU markets and low power mode tailored for smart card/industrial applications. The 16Mb Design test chip (DTC) with industry-leading cell size has demonstrated functionality with tight cell Vt and read current distributions. The SG NVM cell and erase gate are processed with self-alignment to gate spacer and polysilicon CMP (Chemical Mechanical Polishing) that can be easily integrated in a modular way to the standard logic process.

The reliability and failure analysis of high-κ devices plays an important role in CMOS compatible logic and memory devices. Softer stages of dielectric degradation and breakdown deserve in-depth studies given their relevance and finite probability of occurrence in the 14 nm and sub-10 nm CMOS technology nodes of the future. This study presents a multi-physics based percolation framework model to simulate the dynamics of the sequential and competitive evolution of soft breakdown (SBD) spots during degradation of a dual-layer high-κ/ interfacial layer (HK-IL) dielectric stack. The presented model leverages on the combined use of Kinetic Monte Carlo (KMC) routine to describe the microstructural variations and stochastics of defect nucleation and growth as well as the finite element model (FEM) to quantify the spatio-temporal evolution of the potential, field and temperature distributions in the stack. Furthermore, the model reveals a statistic distribution for SBD and a preferential correlation of the breakdown sites to the grain boundary spots.

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Atomic force microscopy was employed to characterize the morphological modifications induced by laser annealing of preamorphized silicon. Laser irradiation was performed at different fluence with fixed pulse durations of 23 ns. In all cases, the laser fluence used is above the threshold fluence that is needed to melt the preamorphized layer. Roughness measurements show that the surface roughness of the silicon samples increases when the laser fluence increases. Since the laser anneal was performed in air, the changes in morphology may be associated with the surface oxide formed. When a high fluence was employed, the extension of melting was sufficient to remove all surface features of the as-implanted sample but apparently there was not enough time to completely redistribute the material upon solidification. As a result, ripple-like periodic structures are formed on the surface. Therefore, a low laser fluence should be used whenever possible in the annealing of silicon samples.

Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2/SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ-interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above/below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Å stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.

This paper addresses the interaction between light wave technologies and semiconductors devices at the nanoscale. Research works aiming at the development of emerging 1D and 2D nano materials such as nanodots, nanowires, nanotubes and nanoribbons open the way to overcome the performances bottleneck of conventional microwave photoconductive switches. Such new materials offer new opportunities for the confinement of light/matter interaction and exhibit interesting energy band diagram in an optical wavelength spectrum covering visible to NIR. Strong material interests stays for the generation of very high local density of carriers in contrast with a high dark resistivity, in association with a high carrier mobility. These challenges can be reached today thanks to nanotechnology processes with a high compatibility constraint with submicrometer light coupling solutions and microwave devices and circuits technologies. Modeling and design tools dedicated to photoconductive effect description at nanometer scale, for its implementation in passive and active components must be set up in order to exalt this effect for microwave signal processing functionalities such as switching, generation, amplification and emission over a large frequency bandwidth. This paper will report on latest demonstrations of high performance photoconductive switches for high frequency applications at 0.8μm and 1.5μm based on LT-GaAs, GaAs nanowires and GaInAsSb semiconductor materials.

The investigated microemulsion system consisted of methyl methacrylate, 2-hydroxyethyl methacrylate and water using sodium dodecyl sulphate as surfactant. Ethylene glycol dimethacrylate acting as a cross-linker was also incorporated to enhance the mechanical strengths of the microporous polymeric materials. The polymerization was carried out at room temperature using a reactive redox initiator comprising ammonium persulphate and N,N,N′,N′-tetramethylethylene diamine. The conductivities of the microemulsion samples were monitored during the course of polymerization. The conductivities for a bicontinuous microemulsion before and after polymerization were found to be very similar. In addition, the transformation of microstructures was also examined using a transmission as well as a field emission scanning electron microscope. It is evidenced from the micrographs that microporous polymeric materials prepared from bicontinuous microemulsion polymerization are attributed to numerous coagulations of spherical particles. A possible mechanism for the microstructural transformation is discussed based on the information of conductivity measurements and electron micrographs. © 1996 John Wiley & Sons, Inc.

Microemulsion systems formulated with methyl methacrylate, 2-hydroxyethyl methacrylate, cross-linking agent, ethylene glycol dimethacrylate (EGDMA) and water using cationic surfactants of n-alkyl trimethyl ammonium bromide with alkyl chain lengths varying from C12 to C16 have been investigated. Photoinitiated polymerization was carried out only for bicontinuous microemulsion samples to form microporous polymeric materials. The opacity of the resulting polymeric materials decreased with the use of shorter alkyl chain lengths of the cationic surfactants. In addition, the morphology of the microporous polymeric solids as observed by Field Emission Scanning Electron Microscope shows a drastic change from worm-like, oval-shaped to globular structures on decreasing the alkyl chain length of the surfactant at a particular concentration. These polymeric materials possessed open-cell structures. Their pore sizes were smaller and their pore volume distributions were narrower for polymer samples using shorter alkyl chain-length surfactants. This study shows the feasibility of controlling the microstructures and pore dimensions of the polymeric materials prepared by polymerization of bicontinuous microemulsions containing different alkyl chain lengths of cationic surfactants.

The feasible control of the microstructures of porous polymeric materials has been studied by polymerization of monomer(s) containing bicontinuous microemulsions. Microstructures of the resulting p...

The microemulsion system comprising water, methyl methacrylate, 2-hydroxyethyl methacrylate, and n-dodecyltrimethylammonium bromide was polymerized and cross-linked with ethylene glycol dimethacrylate. Fast polymerization of the microemulsions to form solid polymers could be easily obtained using dibenzyl ketone as a photoinitiator. Morphology of the resulting polymeric materials formed from bicontinuous microemulsions indicates the existence of open-cell type microporous structures as determined by thermogravimetric analysis. Their pore sizes, as revealed by field emission electron microscope, decreased on increasing the surfactant concentration. This study provides the first simple method for varying the pore size of polymeric materials by microemulsion polymerization of a suitable system using different surfactant concentrations.

Random telegraph noise (RTN) measurements are typically carried out at the device level using standard probe station based electrical characterization setup, where the measured current represents a cumulative effect of the simultaneous response of electron capture/emission events at multiple oxygen vacancy defect (trap) sites. To better characterize the individual defects in the high-κ dielectric thin film, we propose and demonstrate here the measurement and analysis of RTN at the nanoscale using a room temperature scanning tunneling microscope setup, with an effective area of interaction of the probe tip that is as small as 10 nm in diameter. Two-level and multi-level RTN signals due to single and multiple defect locations (possibly dispersed in space and energy) are observed on 4 nm HfO2 thin films deposited on n-Si (100) substrate. The RTN signals are statistically analyzed using the Factorial Hidden Markov Model technique to decode the noise contribution of more than one defect (if any) and estimate t...

Grain boundary (GB) microstructural defects in polycrystalline high-? dielectric thin films may cause localized non-random trap generation during the percolation breakdown (BD) process. We study the effect of this non-random trap generation on the reliability statistics of the metal gate (MG) - high-κ (HK) stack. For the first time, we propose a fundamental physics-based Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of bond breaking, generation of oxygen vacancy traps and simulating the trap evolution process in a dual-layer HK - interfacial layer (IL) gate stack. Our simulation model helps explain the non-Weibull distribution trends for time dependent dielectric breakdown data (TDDB) and also determine the sequence of BD which is found to be independent of the thickness ratio of (t HK : t IL ) and gate voltage (V g ). Results show that the IL layer is always more susceptible to early percolation and circuit level failure may only be caused by multiple soft BD (SBD) events in the IL layer. The possibility of a sequential IL → HK breakdown is very unlikely for operating voltage conditions of V op = 1V.

Grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric materials affect the electrical performance and reliability of advanced HK-based metal-oxide-semiconductor (MOS) devices. In this work, we present a localized study comparing the electrical conduction through grains and GBs for CeO 2 and HfO 2 -based HK dielectrics using scanning tunneling microscopy (STM) and transmission electron microscopy (TEM) at the nanometer scale, in conjunction with macroscopic MOS capacitor device level analysis. Nanoscale STM conduction analysis clearly reveals faster degradation at GB sites and their vulnerability to early percolation. Multi-layer HK dielectric stacks (capping of La 2 O 3 on CeO 2 and dual-layer ZrO 2 /HfO 2 ) are proposed as an effective technique to significantly enhance the time-dependent dielectric breakdown (TDDB) robustness of advanced HK metal gate (MG) stacks.

Dielectric breakdown in advanced gate stacks in state-of-the-art Si nanoelectronic devices has been one of the key front-end reliability concerns for further CMOS technology downscaling. In this paper, we present the latest findings in using physical analysis techniques such as transmission electron microscopy (TEM)/electron energy loss spectroscopy (EELS)/energy dispersive X-ray spectroscopy (EDS), scanning tunneling microscopy (STM) and ballistic-electron-emission microscopy (BEEM) to study the morphology and chemical nature of nanosize structural defects formed in the dielectrics across the different phases of the overall degradation process. The correlation study between the localized physical changes in the material associated with a breakdown path and the electrical characteristics of the device in the post-BD regime is realized by the ultimate resolving power of the high resolution nanoscale physical characterization tools. Various physical defects associated with the trap generation, percolation path formation and post-breakdown wear-out of the dielectric material are identified and studied. The influence and extent of the different types of defects that are responsible for various unique gate current leakage signatures such as random telegraphic noise (RTN), digital-to-analog breakdown transition, switching of percolation conduction and ultrafast transient failure owing to filamentation are reviewed. The implications of the physical studies on the feasibility of advanced high-к metal gate stacks are also addressed.

The paper reports on the fabrication of silicon nanobumps on an n-doped (100) Si wafer with silica microspheres. In the process, a single 248 nm excimer laser pulse was applied on a self-assembled monolayer of 1.5-µm-diameter silica microspheres on a n-doped (100) Si wafer. After laser irradiation at a fluence of 300 mJ/cm2, a regular array of conical Si nanobumps surrounded by a ring shaped trench were fabricated. The structure of the nanobump arrays was characterized by scanning electron microscope, and atomic force microscope. The formed nanobumps were determined to be Si-based bumps with energy disperse spectroscopy. The mechanisms involved in the formation of nanobumps were discussed. The developed Si nanobump pattern has potential applications for sensitive detectors, efficient photovoltaic cells, field-emitter arrays, and displays.The paper reports on the fabrication of silicon nanobumps on an n-doped (100) Si wafer with silica microspheres. In the process, a single 248 nm excimer laser pulse was applied on a self-assembled monolayer of 1.5-µm-diameter silica microspheres on a n-doped (100) Si wafer. After laser irradiation at a fluence of 300 mJ/cm2, a regular array of conical Si nanobumps surrounded by a ring shaped trench were fabricated. The structure of the nanobump arrays was characterized by scanning electron microscope, and atomic force microscope. The formed nanobumps were determined to be Si-based bumps with energy disperse spectroscopy. The mechanisms involved in the formation of nanobumps were discussed. The developed Si nanobump pattern has potential applications for sensitive detectors, efficient photovoltaic cells, field-emitter arrays, and displays.

In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO 2 ) have been replaced by physically thicker high-к transition metal oxide thin films by many manufacturers starting from the 45nm technology node. CMOS process compatibility, integration and reliability are the key issues to address while introducing high-к at the front end. In this study, we analyze in-depth the reliability aspect of high-к dielectrics focusing on both the time-dependent-dielectric breakdown (TDDB) and the post breakdown evolution stage. Electrical characterization, physical failure analysis, statistical reliability modeling as well as atomistic simulations have all been used to achieve a comprehensive understanding of the physics of failure in HK and the associated microstructural defects and failure mechanisms. The role played by different gate materials ranging from poly-Si → FUSI → metal gate and different HK materials (HfO 2 , HfSiON, HfZrO 4 ) is also investigated. Based on the results obtained, we emphasize the need and propose a few approaches of design for reliability (DFR) in high-к gate stacks.

In this work, the electrical activation of Boron in Germanium pre‐amorphized silicon substrate upon flash lamp annealing (FLA) is investigated. We demonstrate that FLA helps in the reduction of the EOR defects, resulting in minimal transient enhanced diffusion and dopant deactivation effect. It has also been observed that the junction stability improves with the increasing number of flash pulses, which is clearly reflected by the dopant deactivation level upon post‐thermal treatment. In another FLA scheme, the spike rapid thermal annealing (RTA) performed prior to the flash further enhances the junction stability. However, this pre‐spike RTA step induces extensive dopant diffusion and an overall degradation in sheet resistance. The above observations are concluded to be due to the different extent of silicon interstitial supersaturation that can be explained by the interactions between the extended defects and dopants. Lastly, leakage current for the junctions formed under different FLA schemes are compared. Typical single pulse FLA junction shows high leakage current and it can be reduced through the additional pulses of FLA or effectively suppressed by the pre‐spike RTA flash scheme. In addition, it is also found that the junction leakage can be correlated to the FLA residual defects. Published version

An additional cleaning technique is implemented in the self-aligned silicide (salicide) process. We discover that logic device yield improves significantly with the additional ammonium peroxide mixture cleaning (APM-clean). This significant improvement is believed to be due to the reduction and tighter distribution achieved in both gate to source/drain leakage and junction leakage. In order to incorporate APM-clean in the salicide process, the stability of both C49 and C54 phase TiSi/sub 2/ in APM solution is studied. We found that C54 phase TiSi/sub 2/ shows good stability in APM solution. On the other hand, C49 phase TiSi/sub 2/ exhibits an interesting line-width dependent etch-rate (/spl ges/1.38 /spl Aring//sec), which resulted in higher sheet resistance.

Electromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.

The spatial distribution of chemical elements is studied in high-κ, metal-gated stacks applied in field effect transistors. Using the transmission electron microscope (TEM)-based analytical techniques electron energy-loss spectroscopy (EELS) and energy-dispersive x-ray spectroscopy, it is demonstrated that Al2O3 and La2O3 capping layers show distinctly different diffusion profiles. The importance of the EELS collection angle is discussed. Popular chemical distribution models that assume La-rich interface layers are rejected.

In this paper, the thermal stability of TiN metal gate with various composition prepared by different preparation technology [(e.g., atomic layer deposition (ALD) or physical vapor deposition (PVD)] on HfO2 high-K dielectric is investigated and compared by physical and electrical analysis. After annealing of the TiN/HfO2 stack at 1000 °C for 30 s, it is observed that: (1) Nitrogen tends to out-diffuse from TiN for all the samples; (2) Oxygen from the interfacial layer (IL) between HfO2 and Si tends to diffuse toward TiN. PVD Ti-rich TiN shows a wider oxygen distribution in the gate stack, and a thinner IL than the N-rich sample. Ti penetration into HfO2 is also observed in the Ti-rich sample, which can potentially lead to the dielectric break-down. Besides, the oxygen out-diffusion can be significantly suppressed for ALD TiN compared to the PVD TiN samples.