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In this paper, gate drive IC for SiC power MOSFETs using soft-switching technique gate drive method is designed and implemented. Designed IC is suitable for driving silicon carbide (SiC) power MOSFET. The gate drive IC using soft-switching gate drive method, which is composed of high side and low side soft-switching controller, reduce the overshoot and switching loss of the SiC power MOSFET during the turn-on period effectively. The gate drive IC using soft-switching gate drive method reduces the switching loss by 14% without increasing the overshoot magnitude. To verify the electrical characteristics of the designed IC, simulations and experiments were performed.

As an efficient patterning method for nanostructures, nanocolloidal lithography (NCL) presents a controllable and scalable means for achieving a uniform and good sidewall profile, and a high aspect ratio. While high selectivity between the etching mask and targeted materials is also essential for NCL-based precision nanophotonic structures, its realization in multi-material nanophotonic structures still remains a challenge due to the dielectric- or metallic-material-dependent etching selectivity. Here, dispersion-controlled Au-NCL is proposed, which enables high selectivity for Al and SiO2 over a Au nanoparticle (Au-NP) mask. Utilizing the proposed process, wafer-scale, uniformly dispersed multi-material nanopawn structures (Au-NPs/Al-SiO2 cylinders) on an Al ultrathin film are realized, obtaining excellent vertical sidewall (≈90°) and aspect ratio (>1). The high sidewall verticality and aspect ratio of the nanopawn structures support optical modes highly sensitive to the excitation direction of incident waves through the mixing of the interface-gap-assisted localized surface plasmons (GLSPs) formed in between the Au-NP and Al-disk interface, and plasmonic Fabry-Perot (FP) modes formed in between the Al-disk and Al substrate; complementary spectral responses between reflected and scattered light are also demonstrated. As an application example, information encryption based on the triple-channel (i.e., reflection, scattering, and transmission) angle-dependent complementary-color responses is presented.

Behavioral studies and protocols are an essential part of neuroscience research. Although mice are one of the premiere model systems for neuroscience, methods that leverage mice’s refined behaviors have only emerged recently. We present here an open-source behavioral platform, with the aim to facilitate adoption and development of behavioral paradigms for mice. The platform is automatized to allow precise control of experimental conditions and increase the reliability and reproducibility of results. It is designed for efficient reward-based learning, and individual components are easily modified to suit the experimenter’s needs. Our platform provides precise measurement and reduces human-induced variability through the use of modern and user-friendly techniques, such as CAD and 3D printing to design and build the platform, and an Arduino microcontroller to timely control the passageways, sensors, the stimuli, and reward delivery. We detail the step-by-step process to set up the apparatus and present a default configuration for a tactile discrimination task. Finally, we discuss its use to investigate touch-based behaviors and their neural underpinnings. This research offers an accessible framework for neuroscience studies aiming to better understand complex behaviors based on the sense of touch.

This paper introduces a mass measurement method and a system for capacitive membrane sensor, which uses the principle of membrane displacement at a resonance frequency which maximizes output voltage due to its strong vibration. The implemented system consists of dedicated hardware, firmware, and PC. The resonance frequencies of the Si3N4 membrane film are 59.2 kHz and 58.2 kHz measured using laser vibrometer and the proposed method, respectively. The resonance frequency of which quartz has a resonance frequency of 32.768 kHz is 32.775 kHz by our method. The suggested method has 600 times more sensitive in measuring the resonance frequency of a capacitive membrane than the conventional static capacitance measurement method.

The disease diagnosis system has been developed using the thin nitride(Si3N4) cantilever arrays which can measure the difference of capacitances between sensor and reference. The system consists of 32-bits RISC(Reduced Instruction Set Computer), RAM/Flash, bus, communication IP's, ADC(Analog Digital Converter) board, and LCD display. The marker selection method, which give us the good accuracy from reasonal numbers of markers, is suggested. The developed system has the resolution under 1fF and can detect 10nM concentration of Thrombin.

Due to the increased complexity of modern embedded systems and time-to-market constraints, a debugger with efficient debugging functions is becoming increasingly necessary, and it plays an important role in the development of application systems. Accordingly, the implementation of efficient debug functionalities must a critical process in the design of a new processor. Since deeply embedded processor cores in a core-based system chip allow only restricted access for debugging its internal status, most recent processors employ the on-chip-based debug method that embeds special logic-supporting debug capabilities. In this paper, we propose an on-chip debug support logic that can be embedded into the processor core to support debug functions. Moreover, we describe an overall implementation method of the on-chip-based processor debugger based on the on-chip debug support logic, which includes a source-level debugger and an interface block. We designed an on-chip debug support logic, and embedded it into a target processor core. We used the GNU Project debugger (GDB) as the source-level debugger of the target processor core. An interface block that uses the remote debugging features of GDB was also developed and that includes a software module and a hardware board. We discuss all major design steps for implementing this on-chip-based processor debugger. We have successfully applied the proposed implementation method to develop the processor debugger for two new 32-bit RISC processors. In addition, we introduce another use of the on-chip-based processor debugger in the design of a processor-based system chip, which can facilitate simulation-based functional verification.

The single-shot dual-energy (DE) method using a sandwich-like multilayer detector generally suffers from noise in the resultant DE images due to the poor quantum noise in images obtained from the rear detector layer and its amplification due to the subtraction operation in DE reconstruction. The use of interlayer metal filter can further increase noise in DE images by increasing the rear-detector quantum noise. We have adopted several noise-reduction algorithms to the single-shot DE reconstruction, which included the Gaussian-filtering noise reduction (GNR), the median-filtering noise reduction (MNR), and the anti-correlated noise reduction (ANR). We assessed the effectiveness of noise-reduction methods by investigating noise and dose-normalized contrast-to-noise ratio for a mouse-mimicking phantom consisting of aluminum bone and polyurethane soft tissues. Noise-power spectrum was also measured to investigate correlation noise. Overall, the ANR showed the best performance. At some extreme imaging technique conditions, such as a lower tube voltages and a larger spectral energy separation using thick copper sheets between the front and rear detector layers, the MNR outperformed the ANR. The performance of GNR was nearly similar to that of MNR. The results were well reflected into demonstration bone images obtained for a postmortem mouse. Although the ANR was effective to reduce noise in the single-shot DE imaging using the sandwich detector, multivariate optimization of ANR parameters with respect to imaging tasks and imaging techniques is remained as a future study.

Recently smart devices which combine traditional electronic devices and personal computers, such as smart phones and smart TV, have caught people`s eyes from all over the world. A multi-media SoC platform which embeds not only a calculating processor but also an operating system could provide an user-customized environment of several types of communication methods to PC or Internet. In this paper, we describe a multi-functioning SoC platform with video, audio and other communicating protocols based on Core-A processor and AMBA buses. To verify the designed multi-media SoC platform, JPEG decoding and ADPCM encoding/decoding algorithms are applied on it and the final decoding results are confirmed by video monitors and audio speakers.

Platform system for measuring the bio-signal, especially Aptamer using array sensor is designed. This platform system is based on 32-bit RISC processor, AMBA bus, peripheral device and interface for array sensors. Array sensors measure a variation of capacitance value by reaction with Aptamer from bio-signal. Processor reduces noise from measured bio-signal and carries out bio-signal processing algorithm.

The noise and vibration of a rotary compressor, a type of multi-input, single output system, are generally studied through frequency analysis. Although this method is effective in analyzing frequency components, using this method to identify the specific source of the noise (4 kHz to 6 kHz) is difficult. Hence, noise source should be studied systematically. In this study, a coherence analysis method based on systems analysis is used to identify the compressor noise source. Compressor noise source is identified through the coherence between the vibration signals on the shell of the compressor and the noise signal at one point near the compressor (1 m away from the compressor). A one-third octave band is employed for frequency analysis. The design of experiment is conducted to identify possible noise factors, such as volume, size, and neck area of the resonator in the compressor cylinder. Analysis showed that noise was generated from the cavity of the cylinder and the muffler inside the rotary compressor. A new type of muffler was applied to the rotary compressor to verify this finding. Noise was dramatically reduced.

Acoustic emission (AE) technology was adopted to the damage diagnosis of thermal barrier coating (TBC) by plasma spray process. These samples were composed of CoNiCrAlY bond layer made by vacuum plasma spray and ZrO 2 -8 wt.%Y 2 O 3 ceramic layer made by air plasma spray on Inconel-718 substrate. To investigate the thermal fatigue damage by high-temperature, the AE signal was measured during four-point bending test followed by cyclic thermal test. The AE monitoring system was composed of PICO type sensor, a wide band pre-amplifier and a DSP board. The AE events, amplitude, cumulative energy, and count were evaluated according to the cycles of thermal fatigue. By AE test, it is shown that AE sources is caused from the stress of thermally grown oxide layer and micro-crack.

The fiber reinforced composite material is widely used in the multi-industrial field where the weight reduction of the infrastructure is demanded because of their high specific modulus and specific strength. It has two main merits which are to cut down energy by reducing weight and to prevent explosive damage proceeding to the sudden bursting which is generated by the pressure leakage condition. Therefore, pressure vessels using this composite material in comparison with conventional metal vessels can be applied in the field such as defence industry, aerospace industry and rocket motor case where lightweight and the high pressure are demanded. In this paper, for non-linear finite element analysis of E-glass/epoxy filament wound composite pressure vessel receiving an internal pressure, the standard interpretation model is developed by using the ANSYS, general commercial software, which is verified as the accuracy and useful characteristic of the solution based on AutoLISP and ANSYS APDL. Both the preprocessor for doing exclusive analysis of filament wound composite pressure vessel and postprocessor that simplifies result of analysis have been developed to help the design engineers.

In this paper, backward extrusion process with low die rotation was studied to improve the problems of conventional backward extrusion process: the requirement of large forming machine, the difficulty in selecting the die material caused by high surface pressure, high cost of forming machine caused by improvement of noise and vibration, etc. In this experiment, model material, plasticine, was used as specimen. The result of torsional and conventional backward extrusions experiment were analyzed and compared by two methods. One is upper bound technique computing velocity field, and another is FEM simulation with DEFORM-3D. In the upper bound analysis, the velocity fields were derived using the dual stream functions. The use of stream functions in formulating upper bound solutions has some advantages. The number of unknown is reduced and incompressibility condition is satisfied. These result show that the torsional backward extrusion is a very useful process because this process yields the homogeneous deformations and lower forming load (decrease about 30%). In this paper, the most proper angular velocity of container is found to be around 0.16 rev/s. But, if the angular velocity was over 0.18 rev/s, deformation pattern was non-uniform and forming load was increased. Due to the decrease in forming load, die life can be improved and it is possible to use a press of relatively low capacity. Also this process can reduce corner cavity and improve the initial cast structure, owing to the high deformation and uniform strain distribution. Additionally, this process might be useful for powder compacting.

Semi-solid forging (SSF) is compared with conventional casting such as gravity die-casting and squeeze casting. A product without inner defects can be obtained from semi-solid forming with a globular micro-Structure. Generally speaking, SSF is composed of reheating, forging and ejecting processes. In the reheating process, the materials are heated up to the temperature between the solidus and liquidus line at which the materials exists in the form of liquid-solid mixture. The process variables such as reheating time, reheating temperature, reheating holding time, and induction heating power have much effect on the quality of the reheated billets. It is difficult to consider all the variables at the same time to predict the quality. In this paper, Taguchi method, regression analysis, and neural network were applied to analyse the relationship between processing conditions and solid fractions. A356 alloy was used, and the learning data were extracted by the reheating experiments. The results of a neural network were in good agreement with experimental results. Polynominal regression analysis was formulated by using the test data from the neural network. An optimum processing condition was derived to minimise the grain size, solid fraction standard deviation, and to maximise the average specimen temperature. Consideration is given to the reheating process of the raw material and results are presented of appropriate process variables for correct solid fraction, specimen temperature, and grain size.

Alumina (Al2O3) powders were synthesized by extracting Al2O3 from kaolin via kaolin-H2SO4 reactions with and without ultrasounds. The amount of Al2O3 extracted from kaolin via the ultrasonic extraction process was investigated by comparing reaction time and reaction temperature with the same factors under the conventional extraction process. The time to obtaining a given amount of Al2O3 by the ultrasonic process was shorter than that by the conventional process, indicating that the application of ultrasound in the synthesis of Al2O3 powders is an efficient way to reduce synthesizing time.

This paper introduces a bio-signal measuring system, which is suitable for array type bio-sensors. The system consists of 32-bits RISC processor, RAM, flash memory, UART, video controller, and ADC module. The system shows that the maximum difference of each chanel capacitance without sensor loading is under 1fF. The system is used for liver cancer dection because it has an inteligence about the disease through a neural network.

This paper presents a digital controller with a new dimming method for LED driver core circuits. The designed circuit enables the LED driver operate without a bulky capacitor and voltage dividing resistors. The proposed digital controller circuit was designed and fabricated using the 1 µm-650 V DMOS process. The results obtained from the simulation and measurement of the chip indicate that the inductor current waveform is similar to the input voltage to gain a high power factor, because the inductor current is synchronized to the zero voltage signal as expected.

In this paper, we introduce a method to find useful markers from sensor arrays which have massive sensing points and diagnose liver cancer based on machine learning algorithms which are neural network and fuzzy neural network. We obtain reliable results by using a learning ability and n-fold cross validation. For the verification of the proposed method, raw data of serums from 314 normal and 81 patients reacted to 1,142 aptamers are used. According to the results, we can detect liver cancer with the accuracy of 99.19 % by average use of 132 aptamers based on neural network and 98.19 % by average use of 226 aptamers based on fuzzy neural network.

An investigation has been performed into the effect of the die and deformation pattern on twist-assisted upset forging. Rotation of the lower flat die accompanied by axial compression of the punch plays a distinct role in saving axial force. In this study, an upper bound analysis considering bulge formation, finite element method simulations (DEFORM 3D) and experimental research were carried out. A simple kinematically admissible velocity field for three-dimensional deformation is presented for twist-assisted upset forging of a cylindrical billet. An analytical expression for the upset force and torque is obtained from several process parameters. An increase in the friction factor and rotation speed was found to favour decreases in the magnitude of the upset force, dead metal zone and non-homogeneous deformation. Plasticine model experiments were performed where the lower die was rotated against the workpiece using a 5 ton model press.

In a conventional upset forging, the presence of friction at the tool–workpiece interface not only increases the forging pressure and force, but also leads to non-homogeneity of deformation. In this study, to solve the above problems, a parametric study is presented on a new rotational upset forging process. Twisting torque can change the harmful effect of friction into a useful effect. Experiments were carried out to generate data of forming parameters, which are the friction factor, the sliding factor, the punch velocity and the geometry of the billets, on the rotational upset forging process. Comparing with the conventional upset forging process, the rotational upset forging process reduces both the forming load and bulging. The deformation of rotational upset forging is more uniformly distributed and its total deformation is greater than that of conventional upset forging for the same reduction of height.

Many products related to the automobile and airplane industries have been manufactured by semi-solid forming. In this paper, finite element analysis of the product of combined extrusion of semi-solid material was performed and its experimental verification using A356 was conducted. The analysis distribution of the solid fraction was investigated and compared with the experimental microstructure in the product. In addition, the distribution of temperature in the product was analyzed by finite element analysis. This paper also presents the forming process of the combined extrusion of semi-solid material.

It is already known that the hardness number of a cold-forged product is closely related to its effective strain. This paper presents a method of predicting the relation between effective strains and hardness by using an FE- hardness test simulation based on the concept that hardness indicates resistance to plastic deformation. The results of the FE-simulation for the materials are compared with those of experiments and also with those of experiments purporting to show the feasibility of the proposed method.

In semi-solid forging, it is necessary to control the forming variables accurately in order to make near net shape products. Generally, the defects of products may occur due to liquid segregation that can be caused by deformation, strain rate, and condition of friction. The liquid segregation is to be predicted by flow analysis. This paper presents upper bound analysis model using the new yield function proposed by Doraiveluet al. The model has been applied to analyze the simple compression process of semi-solid Sn-15%Pb alloys to confirm the usefulness of the yield function. The radial distribution of the liquid fraction at various strains, strain rates, and friction conditions between die and workpiece has been estimated.

In this letter, a fiber Raman amplifier (FRA) design method enabling the simultaneous control of the gain and noise figure (NF) spectra, is proposed. By constructing the FRA with predetermined target forward/backward gain spectra, the spectral error function of NF is calculated, to determine the pump power combination satisfying both the targeting gain and NF spectra. The FRA gain/NF design within 0.1 dB of accuracy is demonstrated for various shapes of target spectra

 Abstract—Nowadays, the SoC is concentrated by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. As the complexity of SoC design increases with technology development, the observability of the SoC's internal state is no longer easy to achieve. Because of the above reasons, debugging the SoC system becomes very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we deal with implementation of a hardware debugger named OCD2G which is based on IEEE 1149.1 JTAG standard and supports halt-mode and monitoring-mode debugging. In order to verify the operation of OCD2G, the designed debugger is integrated into the 32bit RISC processor - Core-A (Core-A is an embedded processor designed in South Korea) and is tested by interconnecting with software debugger.

Bio-signal processor platform system carries out the bio-signal processing extracted from array sensors. This system consists of 32-bit RISC processor, data converter circuit, array sensors and bio-signal processing algorithm. The designed specific processor includes CPU functional blocks and memory. Array sensors measure a variation of capacitance value by reaction with DNA, aptamer and protein. Processor reduces noise component from measured bio-signal and compares and detects disease by analyzing properties of bio-signals.

This paper deals with the design and implementation of the 16-bit fixed point digital signal processor. The designed DSP has 211 instructions and consists of 40-bit ALU, 6 level pipelines, 17-bit X 17-bit parallel multiplier for single-cycle MAC operation, 8 addressing modes, 8 auxiliary registers, 2 auxiliary register arithmetic units, two 40-bit accumulators and 2 address generators. The verilog HDL coded synthesizable RTL code of the DSP core has a complexity of 69,860 in the two input NAND gates. We verified the functions of the DSP by a simulation with a single instruction test as the first step. and then implemented the DSP with the FPGA. The test vectors have a single instruction test, combination of single instructions and algorithm applications, ADPCM vocoder and the MP3 decoder. After FPGA verification, the DSP core is fabricated with 0.25 um CMOS technology. The DSP core carried out three test vector sets which are tested at FPGA at the 106 MHz clock rates.

In this paper, we introduce on-chip debug system (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (on-chip debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32 bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(joint test action group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.

Many processors for embedded system have been developed and is widely being used in many industrial area. If we develop a new embedded processor, we need a simulator, compiler, and debugger for developing an operating system and basic program running on the embedded processor. The debugger is used for finding the error in a program. theses software are very important in embedded system. In this paper, we design and implement a retargetable software debugger for a new 32-bit microprocessor. Our software debugger is based on GNU debugger (GDB) which is a widely used open-source debugger. We explain how to develop a retagetable software debugger for a new embedded processor rapidly. In order to develop a debugger rapidly, we extended only processor-dependent modules for register, memory and instruction set. And, we reused the processor-independent modules in the debugger. In the experiment, we tried to compare our software debugger with ARM AXD debugger to verify the debugger operation. The ARM AXD Debugger is well-known debugger for ARM processor.

This paper deals with the timing acquisition for ultra wideband (UWB) signals in dense multipath environment. To estimate the start of the frame with respect to the receiver's clock, least square (LS) method has recently proposed. However, that method needs accurate channel length for precise timing. In our proposed algorithm, we estimate the effective channel length by estimating the root mean square (RMS) delay spread of noisy template (NT). The results show that our proposed method has better performance than conventional correlation methods due to the improved timing acquisition.

This letter proposes a novel on-chip step-dimmer using an analog dimming method for a high PF AC-powered LED driver. The full AC LED driver can achieve a very high PF and a low THD by using a self-adaptive power processing circuit while delivering a best-in-class dimming performance with the proposed step-dimmer. Under the control of the dimming signal, the dimming voltage is step-adjusted from 1.0V to 2.5V, the average LED current can be changed from 40% to 100% of the nominal LED current value. To verify the feasibility of the proposed scheme, an 8-string 4.4WAC-powered LED driver with the proposed step-dimmer was designed and simulated using a 0.35 um-700V BCD Magnachip process. The gained results verify that the proposed step-dimmer can maintain a high performance of the AC LED driver under different dimming modes with a PF and a THD around 0.998 and 6%, respectively.