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Transfer printing of micro-LED pixels from flexible SWP tape to a less adhesive thiol-modified rigid substrate is assisted by using a PS sacrificial layer. This may be of essential value in mass transfer technology for display applications.

Micro-LEDs are one of the most promising candidates for next-generation displays, yet they are inconvenienced by the efficiency reduction induced by the sidewall defects when pursuing further scaled-down device dimensions. We have systematically investigated both the size and temporal dependence of micro-LEDs. Micro-LED arrays with a mesa size ranging from 7 to 100 μm were prepared for display purposes. The luminance and external quantum efficiency (EQE) were measured and discussed. Surprisingly, micro-LED arrays with a smaller mesa size exhibit a higher EQE under 100 ns pulse duration operation when compared with longer pulse duration operations. Under certain short-pulsed excitation, a 7×7 μm2 micro-LED array even exhibits a >20% higher EQE as compared to the direct current (DC) or the long duration pulse operation condition. We thus concluded that the notorious efficiency reduction induced by sidewall defects in small-sized micro-LED arrays could be significantly reduced by applying short-pulse voltages.

Deep reactive ion etching (DRIE) technology is one of the most important technologies in the processing of microelectronic devices and microelectromechanical system. As a necessary process in semiconductor integration, it has been widely studied in the past decades. It is known that the traditional DRIE process typically uses a plasma etching reactor equipped with inductively coupled plasma (ICP) sources to generate a high-density plasma so as to achieve high aspect ratio trenches with relatively small roughness. A cryogenic temperature control unit is typically employed as well. Here, however, we use a parallel plate RIE with rather simple structure, which is not usually used for DRIE, to obtain high aspect ratio silicon etching. With no ICP sources and no sophisticated temperature control unit, the system and experiment are now much more cost effective. Through the optimization of the processing, the etching rate of silicon can reach 440 nm/min. Finally, a 45 μm deep trench is etched in silicon with good perpendicularity. This method will greatly reduce the equipment related cost, especially for those applications that do not have extremely stringent requirement on the final etching accuracy.

For the purpose of studying the effect of high-density, small-size solder joints on the thermal fatigue life of display devices, a 3D model of the corresponding device structure is established, using finite element analysis methods, and using Anand constitutive equations and Coffin-Manson life prediction models. The equivalent stress and strain change law of an indium solder joint with a diameter of 10 μm under thermal cycling loading conditions is explored, and the key position of the solder joint damage is inferred based on the simulated strain cloud diagram. In addition, the influence of different bump height, bump contact area and Under-Bump Metallization (UBM) thickness on the thermal fatigue life of solder joints is studied separately. The final simulation results show that the location where the solder joint may be damaged first is at the point on the outer side where the solder joint is connected to the UBM on the edge away from the center point. The height of the bump and the contact area of the bump have a significant effect on its thermal fatigue life. In the actual experiment, we should focus on the impact of this aspect.