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412 results on '"Jung-Hwan Choi"'

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1. Opponent vesicular transporters regulate the strength of glutamatergic neurotransmission in a C. elegans sensory circuit

2. The Impact of Atrial Left-to-Right Shunt on Pulmonary Hypertension in Preterm Infants with Moderate or Severe Bronchopulmonary Dysplasia

3. Enterostomy Closure Timing for Minimizing Postoperative Complications in Premature Infants

4. A case of mucolipidosis II presenting with prenatal skeletal dysplasia and severe secondary hyperparathyroidism at birth

5. A case of McKusick-Kaufman syndrome

6. Decreased heart sound in a healthy newborn: Spontaneous multiseptated cystic pneumomediastinum with delayed respiratory distress

9. Usefulness of a drill stopper to prevent iatrogenic soft tissue injury in orthopedic surgery

10. Complexity-Aware Layer-Wise Mixed-Precision Schemes With SQNR-Based Fast Analysis

11. A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.

14. 13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.

15. A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application.

18. A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process.

20. A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.

21. Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.

22. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.

23. A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.

27. A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

30. A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.

31. A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.

33. 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

35. 23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.

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