412 results on '"Jung-Hwan Choi"'
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2. The Impact of Atrial Left-to-Right Shunt on Pulmonary Hypertension in Preterm Infants with Moderate or Severe Bronchopulmonary Dysplasia
3. Enterostomy Closure Timing for Minimizing Postoperative Complications in Premature Infants
4. A case of mucolipidosis II presenting with prenatal skeletal dysplasia and severe secondary hyperparathyroidism at birth
5. A case of McKusick-Kaufman syndrome
6. Decreased heart sound in a healthy newborn: Spontaneous multiseptated cystic pneumomediastinum with delayed respiratory distress
7. A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.
8. A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques.
9. Usefulness of a drill stopper to prevent iatrogenic soft tissue injury in orthopedic surgery
10. Complexity-Aware Layer-Wise Mixed-Precision Schemes With SQNR-Based Fast Analysis
11. A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.
12. A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.
13. A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE.
14. 13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
15. A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application.
16. A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor.
17. SQNR-based Layer-wise Mixed-Precision Schemes with Computational Complexity Consideration.
18. A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process.
19. An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM.
20. A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.
21. Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.
22. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
23. A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
24. A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend
25. A 6-Gb/s PAM-3 Transceiver With Background Time-Varying Offset Sensing and Compensation
26. Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning
27. A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
28. Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
29. Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC)
30. A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.
31. A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.
32. 17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.
33. 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.
34. 23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
35. 23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.
36. A 0.95pJ/b 5.12Gb/s/pin Charge-Recycling IOs with 47% Energy Reduction for Big Data Applications
37. A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation
38. A Digital Temperature Sensor Based on 10b SAR ADC for Non-linear Temperature Dependency Compensation in 3D NAND Flash Memory
39. Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm
40. Improved clock-gating control scheme for transparent pipeline.
41. A Spatial Correlation Model for Shadow Fading in Indoor Multipath Propagation.
42. Enhanced Westwood as per Vegas-Based Estimator with Slowstart Threshold for High-Speed Networks.
43. O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.
44. A process variation aware low power synthesis methodology for fixed-point FIR filters.
45. The effect of process variation on device temperature in FinFET circuits.
46. Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
47. Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
48. Speed binning aware design methodology to improve profit under parameter variations.
49. A Low EMI characteristic of LPDDR5 SDRAM with Edge-placed PADs and Short Re-Distribution Lines
50. A low power capacitive coupled bus interface based on pulsed signaling.
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