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The capacitively coupled instrumentation amplifier (CCIA) is broadly used for neural signal acquisition. Although it is suitable for various biopotential recording applications, the CCIA is vulnerable to capacitor mismatches, which degrades the common-mode rejection ratio (CMRR). The neural signals with small amplitude can be easily contaminated by large-amplitude common-mode (CM) interferences due to the degraded CMRR. This brief presents a CMRR enhancement circuit for the CCIA, with which the capacitor mismatches can be compensated in a power-efficient manner. In the proposed CCIA, the gains of a pair of output stages are controlled separately to reject the output signals generated by the CM interferers in the presence of capacitor mismatches. Employing the proposed CMRR enhancement scheme, the implemented CCIA achieves a CMRR over 90 dB from 10 Hz to 1 kHz and 3.4- $\mu \text{V}_{\mathrm{ rms}}$ integrated input-referred noise (IRN) while only consuming $1.5~\mu \text{W}$ per channel.

The bidirectional neural interface is essential to realize the closed-loop neuromodulation, which is the core of next-generation neurological devices. For the bidirectional neural interface, a recording circuit with a high dynamic range (DR) is required to record the neural signal while stimulating the neuronal cells simultaneously. This article presents a voltage-controlled oscillator (VCO)-based neural-recording IC, which directly quantizes the input signal and achieves a large DR to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit ( $G_{\mathrm {m, in}}$ ) by using a resistor digital-to-analog converter (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance ( $Z_{\mathrm {in}}$ ). The implemented neural-recording IC achieves 81.3-dB SNDR over 200-Hz signal bandwidth and 200-mVpp maximum allowable input range with consuming 3.9 $\mu \text{W}$ per channel. The in-vitro measurement with prerecorded neural signal demonstrates that the original neural signal is well preserved in the presence of the large-amplitude artifact without any saturation or significant distortion.

Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 \Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.

In recent years, buck-boost converters have been widely utilized for battery-powered mobile systems such as RF power amplifiers, battery chargers, and LED drivers. However, in a wide battery voltage range, they face challenges including dynamic voltage scaling (DVS), wide load current range, and dynamic line/load transients while ensuring reliability for an industrial usage. To resolve these issues, the conventional buck-boost (CBB) converter should overcome the characteristic of discontinuity in the output transfer current (OTC) which causes degradation of loop dynamics and transient response. Several past works with continuous OTC have been proposed to resolve these problems, but their voltage conversion ratios are limited [1], [2]. Moreover, in [3], [4], a high-voltage (HV) process, which necessitates large active area and incurs high fabrication cost, is required to withstand voltage stresses over 10V (2×V IN ) applied across power switches. To overcome the above challenges, this paper proposes a voltage-tolerant three-level buck-boost (TLBB) converter. The TLBB has continuous OTC and uses only normal 5V CMOS devices for its switches. In addition, a voltage-tolerant dual channel-interleaved three-level buck-boost (DTLBB) converter is suggested for applications [5] requiring a wide range of load current and high conversion ratio while supporting fast DVS transition.

This paper presents a phase-cut dimmable ac–dc buck LED driver for electrolytic capacitor-less LED lighting applications. In the driver, the sine-reference band (SRB)-controlled average current technique is proposed to perform rectified sine-average current control and phase-cut dimming control. The rectified sine-average current control can regulate the average value of sine-wave LED current, maintaining a high power factor (PF) over a wide range of ac input voltage and output LED load. The phase-cut dimming control not only makes the LED driver compatible with two types of phase-cut dimmers, namely, leading-edge and trailing-edge dimming types, but also eliminates visible dimming flicker at the ac line frequency. Fabricated in a 0.35 μ m CMOS process, experimental results show the line regulation of ±2.36% over 90 to 260 VAC and the load regulation of ±0.65% within the load range of 10 to 36 LEDs. The PF exceeds 0.95 under all conditions, and the peak efficiency of 90.7% is achieved. The analysis of the flicker frequency verifies that the proposed dimmable LED driver completely eliminates visible flicker owing to the phase dimming variations without an output electrolytic capacitor.

A high-signal-to-noise ratio (SNR) inductor-free 3-D hover sensor is presented. This paper solved the low-signal component issue, which is the biggest problem in 3-D hover sensing. For this purpose, we propose a power- and cost-effective high-voltage driving technique in the self-capacitance sensing scheme (SCSS) and lateral resolution optimization of a touch panel. In addition, the huge panel offsets in the SCSS from both vertical panel capacitance (CSV) and horizontal panel capacitance (CSH) can effectively be eliminated by exploiting the panel’s natural characteristics, without using other costly resources. Therefore, in the proposed design, the total calibration block is minimized only for parasitic capacitance mismatches. Last, by adopting new driving scheme, two-phase simultaneous sensing is enabled to increase the SNR further. The proposed hover sensing system achieved a 39-dB SNR at a 1-cm hover point under a 240-Hz scan rate condition in noise experiments, while consuming 183 $\mu \text{W}$ /electrode and 0.73 mm2/sensor, which are the lowest power per electrode performance and the smallest die-area per sensor performance, respectively, in comparison to the state-of-the-art 3-D hover systems.

This letter presents a 2-phase 3-level (2P3L) envelope tracking supply modulator (ETSM) for a long-term evolution 20 MHz (LTE20) radio frequency power amplifier as a solution for the ET system. This 2P3L ETSM that is composed of only switching converters achieves high efficiency, fast transient response, and a small output current ripple. To properly operate the proposed 2P3L ETSM, 4 pulse width modulatiop (PWM) signals with a 90° phase shift from each PWM signal are required without any mismatch between duty cycles. To remove the mismatch, a time-division multiplexing comparator and a duty-cycle calibrator are proposed. Thanks to the proposed techniques, the proposed ETSM fabricated in 0.18-μm CMOS achieved the highest peak dynamic efficiency of 88.6% with an LTE20 signal, which is superior to the state-of-the-art systems.

This paper presents a readout method and circuit for large, capacitive-type touch-screen panels (TSPs). Despite the considerable amount of RC time delay of large-area TSPs, the proposed readout method with a receiver (Rx) input series-capacitor improves the settling speed of signals transferred from the transmitter (Tx) to the Rx, by reducing the RC time delay. Combined with the Rx input series-capacitor, a capacitive-input fully differential filtered charge integrator effectively cancels out the display noise and reduces the self-noise in capacitive-type TSPs. The proposed Rx circuit was implemented using 0.35- $\mu \text{m}$ CMOS. Using a 65-in metal-mesh TSP with 169 Tx and 97 Rx electrodes mounted on a liquid-crystal display for testing, the proposed readout method achieved 65% reduction of signal settling time within an accuracy of $\geq 3\tau $ for the longest signal path of the TSP. Using the RC time delay reduction technique, the Tx driving frequency could be boosted by as much as 400 kHz, and the measured signal-to-noise ratio of 43.5 dB was obtained for finger touch at a 120-Hz scan rate, resulting in a figure-of-merit of 0.26 nJ/node, while the overall power consumption was 76 mW.

In the recent 3GPP standard, 5G New Radio (NR) in the sub-6GHz frequency band supports up to 100MHz bandwidth (BW) for uplink channel and requires fast on/off transition below $10 \mu \mathrm {s}$ to support short transition-time interval (TTI). Thus, it forces the supply modulator (SM) to track the NR-100MHz envelope signal for power saving of an RF power amplifier (RF-PA) and requires a fast dynamic voltage-scaling (DVS) transition. For the 3G/LTE uplink, the SM has to satisfy low receiver-band noise (RxBN) for LTE-FDD bands [1] and a boosted output for Power Class 2 high-power user equipment (HPUE) in TD-LTE [2], [3]. In order to support the 100MHz envelope tracking (ET) BW, the SM must have a 3dB bandwidth of at least 125MHz while keeping sufficient phase margin in the presence of few-hundred-pF load capacitance. Furthermore, a typical linear-assisted SM topology has maximum efficiency limitation due to the AB bias current, sinking- and sourcing-current of the linear amplifier. In this work, a voltage-buffer-compensated (VBC) Class-AB linear amplifier (LA) and a feed-forward fast-switching (FFFS) buck converter are proposed to achieve the 100MHz ET BW and high system-power efficiency.

An active matrix organic light emitting diode (AMOLED) display driver IC, enabling real-time thin-film transistor (TFT) nonuniformity compensation, is presented with a hybrid driving method to satisfy fast driving speed, high TFT current accuracy, and a high aperture ratio. The proposed hybrid column-driver IC drives a mobile UHD $\left({{3840} \times {2160}} \right)$ AMOLED panel, with one horizontal time of ${7}.{7}\,{\upmu \text{s}}$ at a scan frequency of 60 Hz, simultaneously senses the TFT current for back-end TFT variation compensation. Due to external compensation, a simple 3T1C pixel circuit is employed in each pixel. Accurate current sensing and high panel noise immunity is guaranteed by a proposed current-sensing circuit. By reusing the hybrid column-driver circuitries, the driver embodies an 8 bit current-mode ADC to measure OLED $V$ – $I$ transfer characteristic for OLED luminance-degradation compensation. Measurement results show that the hybrid driving method reduces the maximum current error between two emulated TFTs with a 60 mV threshold voltage difference under 1 gray-level error of 0.94 gray level (37 nA) in 8 bit gray scales from 12.82 gray level (501 nA). The circuit-reused current-mode ADC achieves 0.56 LSB DNL and 0.75 LSB INL.

This paper presents a 5-bit VCO-based neural recording IC, which directly quantizes the input signal and achieves a large dynamic range (DR) to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit (Gm,in) by using a resistor DAC (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance (Z in ). The implemented neural recording IC achieves 813dB SNDR over 200Hz signal bandwidth and 200mV PP maximum allowable input range while consuming 3.9μW per channel.

This paper presents a direct-digital-conversion biopotential-recording front-end with 92.3dB dynamic range at an input range of $360\text{mV}_{\text{pp}}$. The proposed front-end is a capacitively - coupled 3rd-order Gm-C CT $\Delta\Sigma \text{M}$ with a 5-bit SAR quantizer. The capacitively-coupled summing circuit increases linearity of the $\Delta\Sigma \text{M}$, and a 3rd-order Gm-C loop filter and a 5-bit SAR ADC reduces quantization noise level. The proposed front-end is fabricated in $0.18\mu \text{m}$ CMOS, and achieves 91.3dB SNDR and $1.8\mu \text{V}_{\text{rms}}$ input-referred noise over 100Hz BW. Also, an in-vitro LFP recording is performed to verify the front-end.

This paper presents a comparator-based Quasi-Digital LDO (QDLDO) for the negative supply which has an ultra-fast transient response for the PCRAM systems. Even under the sharp spike of a load current having a peak value of 80 mA with a short rising time of 2.5 ns, the QDLDO effectively minimized a voltage spike on the output voltage, reducing it to 150 mV within only 40 ns. With I/O transistors to withstand I/O voltage stress, this LDO achieved the bestFOM of 0.042 V/um2, among the other state-of-the-art LDOs fabricated in more advanced technologies.

An error-based control method is proposed for a single-inductor multiple-output (SIMO) converter that maintains high efficiency under various load conditions. A peak efficiency of 88.7% was achieved with one output $({\rm I}_{{\rm O}1})$ of 5 mA, while the other outputs are at 432 mA. A hybrid topology composed of a switching converter and a linear regulator is also presented for fast load transient response. The proposed SIMO buck converter was fabricated with a 1P4M 0.35 $\mu$ m BCD process and has 10 independently regulated outputs. The measured load transient waveform shows cross regulation of 0.1 mV/mA and a load transient of 0.17 mV/mA. This was achieved under load transient conditions for one output $({\rm I}_{{\rm O}9})$ in between 1 mA and 100 mA with the other outputs at 422 mA.

This paper presents a high SNR self-capacitance sensing 3D hover sensor that does not use panel offset cancelation blocks. Not only reducing noise components, but increasing the signal components together, this paper achieved a high SNR performance while consuming very low power and die-area. Thanks to the proposed separated structure between driving and sensing circuits of the self-capacitance sensing scheme (SCSS), the signal components are increased without using high-voltage MOS sensing amplifiers which consume big die-area and power and badly degrade SNR. In addition, since a huge panel offset problem in SCSS is solved exploiting the panel's natural characteristics, other costly resources are not required. Furthermore, display noise and parasitic capacitance mismatch errors are compressed. We demonstrate a 39dB SNR at a 1cm hover point under 240Hz scan rate condition with noise experiments, while consuming 183uW/electrode and 0.73mm2/sensor, which are the power per electrode and the die-area per sensor, respectively.

This paper presents a dual-source energy harvesting circuit that efficiently and simultaneously extracts the energy from a piezoelectric transducer (PZT) and a thermoelectric generator (TEG). The harvester operates in a dual-source pile-up mode (DPM) to efficiently extract the energy from both sources with an increment of the damping force, resulting in a 1452% improvement of power extraction even without a TEG, which is the best among the-state-of-the-art works. Also, the harvester operates in a boost converter mode (BCM) without an additional power switch, achieving 75 % conversion efficiency at 450 μW output power. With a single-shared inductor, a simple control scheme enables the harvester to operate in both DPM and BCM by a time-multiplexing method, consuming low quiescent current of 240 nA.

As the portable device market tries to enhance user experience, high-power audio systems with boosted supply voltage have been the main design focus recently. Several past works have addressed issues related to boosted supply voltages [1,2]. Nevertheless, the power stage retained the classical H-bridge structure in the previous works, which resulted in aggravated electromagnetic interference (EMI) from high switching amplitude and poor efficiency due to voltage boosting. The use of multi-level pulse-width modulation (PWM) shown in Fig. 5.2.1 can naturally eliminate the complications caused by high supply voltages. Since the audio signal has a high crest factor, a multi-level Class-D amplifier draws most power directly from a low-voltage battery source, which in turn improves the power efficiency significantly [3]. Spread spectrum techniques prevent energy localization in the power spectral density [2]. Nevertheless, the diffusion of switching harmonics into the nearby frequencies complicates EMI management. However, the multi-level switching scheme suppresses EMI by reducing the switching amplitude without spreading the energy spectrum [4]. In this work, a new folded-PWM (FPWM) architecture implementing a multi-level H-bridge topology is presented.

The number of mobile device users increases every year. Each mobile device is usually equipped with a Li-ion battery having voltage that varies from a minimum of 2.7V to a maximum of 4.2V. Therefore, as the battery voltage decreases with time, a DC-DC converter is required for a regulated supply lower or higher than the battery voltage. A simple buck converter is not suited for this case, since step-up conversion is not available [1]. Instead, a non-inverting buck-boost converter can be a solution over the entire range of the battery voltage [1–4]. Many research studies related to buck-boost converters operated on Li-ion batteries set the target output voltage at around 3.4V [3,4]. Since Li-ion batteries have a wide plateau from 3.6V to 3.8V and a small energy storage below the plateau, DC-DC converters are generally operated on step-down mode at most of the battery voltage range, as shown in Fig. 10.4.1 top. Notwithstanding, step-up conversion is also required for extracting the energy below the plateau even if it is a small amount in the battery. Therefore, in DC-DC converters, it is critical to maintain high efficiency over the whole range of the battery voltage when it operates on both step-down and step-up modes to prolong the battery usage effectively. However, if the conventional buck-boost topology of Fig. 10.4.1 bottom-left is used for step-up and step-down purposes, there are always two switches (S 1 and S 3 ) conducting in the main current path through the inductor. Thus, the switches become large in size to minimize the conduction loss. As the switching loss also increases when the switch size is larger, the efficiency of this structure is usually lower than that of the simple buck (or boost) converter [1]. In this respect, this paper proposes a topology named a flying-capacitor buck-boost (FCBB) converter suitable for such an application by obtaining both step-up and step-down operations with high efficiency throughout the whole range of the battery voltage.

This paper describes the design of a gamma-type current-mode digital-to-analog converter (DAC) for active-matrix organic light-emitting diode display (AMOLED) drivers. The proposed nonlinear DAC is composed of division-based bypassing DAC units for gamma correction. This multiple stack of DAC units dramatically reduces the chip size of the display driver while realizing more natural gamma correction. Moreover, it does not require an additional memory, such as a digital look-up table block and a DAC with a higher resolution, which can achieve significant manufacturing cost savings. Consequently, the proposed multi-stacked gamma-type DAC provides high area efficiency, low cost, and more natural gamma correction. The prototype 8-bit DAC is implemented in a TowerJazz 3.3 V CMOS process. The simulated gamma values of the double- and triple-stacked DAC units are varied from 1 to 2 and from 1 to 3, respectively. In addition, the Monte-Carlo simulation demenstrates that the proposed design shows uniform gamma tra...

A real-time compensation method for TFT variation is proposed for AMOLED displays. This method enables a column driver to sense TFT current of each pixel using a power line as a current sensing line while driving a pixel without increasing a scan time. A fast OLED degradation sensing is also possible to compensate the image sticking problem. A target application of the proposed driver is a simultaneous emission full-HD AMOLED TV, whose scan time is 7.5μs at a scan frequency of 120Hz.

This paper presents a reconfigurable SIMO system with 10-output dual-bus DC-DC converter having two buses for heavy and light load outputs, respectively. The converter controls the load condition for each bus to be well balanced. Under diversified load condition, a group allocator assigns each output to the corresponding bus properly depending on its load current. Due to such load balancing function, severe regulation issues which could occur under diversified load condition are resolved with output voltage ripples below 25mV, and over 81% efficiency is achieved under wide range of load (0–300mA).

A phase-cut dimmable AC-DC buck LED driver is presented with a sine-reference band (SRB)-controlled average current technique as a new control scheme. The proposed SRB-controlled average current technique can perform both sine current control and phase dimming control. The sine current control regulates the average LED current as a sine-wave maintaining high power factor. The phase dimming control removes visible flicker at AC line frequency without an electrolytic capacitor and makes the driver compatible with two types of phase-cut dimmer. Experimental results show line regulation 0.95, and 90.7% peak efficiency.

As the panel size and resolution of flat-panel displays grow, the one-horizontal (1-H) time, in which a column driver should program data voltage into a row of pixels, is reduced and becomes a main bottleneck to realize high-resolution displays [1]. An ultra-high-definition display (UHD, 3840 RGB × 2160) requires column drivers to program the data voltage within the 1.8µs 1-H time required for a frame rate of 240Hz. However, the settling time from the driver to the pixel is strictly limited by display panel load resistance (RL) and capacitance (CL). Also, the RLCL delay becomes larger as panel size grows. Although a dual-driving method, in which the column drivers are assembled at both ends of columns, can double the 1-H time and reduce the RLCL delay by a factor of 4, it increases the bezel width and cost of a display device. To overcome the RLCL delay and reduce the settling time, pre-emphasis driving methods have been proposed [2–4]. However, the common problem of previous works is that the settling time can vary widely under column-to-column RLCL variation as depicted in the waveform in Fig. 11.7.1. The graph in Fig. 11.7.1 plots the settling time of the data voltage (vD) to the end of the data line (vP) within 0.7% of ΔV for four different values of K from a behavioral simulation. The settling time can be even longer with a smaller RLCL. This is because the pre-emphasis factor K (the ratio of an overdriven voltage step (K·ΔV) to a data voltage step (ΔV)) and the pre-emphasis duration (TPRE) are globally fixed. This CLeaRLy shows that the settling time with a fixed K and the K value for the point of the shortest settling time significantly changes according to the column-to-column RLCL variation, which cannot be measured for each column because of the large number of columns (3840×3) in the UHD display panel. Moreover, the K value, determined by passive components such as the method in [2], can suffer from process variation among channels. This also results in settling time variation.