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Flexible capacitive sensor devices have gained attention because of their versatility and adaptability to several requirements. However, the proper implementation of those devices into flexible electronic systems imply some challenges related to the readout strategies necessary to adequately determine capacitance values. Usually, electronic circuits are used to develop signal conditioning and processing tasks, as well as estimation of parameters. In this study, a free‐of‐signal conditioning strategy for capacitance measurement based on an algebraic parameter identification approach is presented. Furthermore, flexible capacitors over polyethylene terephthalate substrates and polydimethylsiloxane as dielectric material are fabricated with the aim to validate the behaviour of the capacitance measurement method. Experimental results are compared with standard recursive least square technique as well as standard capacitance metre. Overall results demonstrate the good performance of the proposed approach.

The manufacturing of electronic devices over flexible substrates becomes a very interesting approach for novel applications. However, the possibility to implement the full technological fabrication procedure is limited for the thermal properties of the flexible substrates. In this paper, the synthesis of zinc oxide nanoparticles by solvothermal process at three different temperatures is presented. Nanopowders synthetized at different temperatures by the solvothermal process were characterized by X-ray diffraction, UV–Vis spectroscopy, and scanning electron microscopy, SEM. Characterization results show that, ZnO powders present a hexagonal wurtzite structure, a band gap magnitude around 3.28 eV, and the particle size is reduced as the temperature is increased. Additionally, fabrication of Schottky barrier diodes based on zinc oxide nanoparticles over polyethylene terephthalate (PET) substrates is shown. The maximum temperature used in the diode fabrication was 150 °C, which is compatible with flexible substrates. Electrical characterization of fabricated diodes showed the thermionic emission as the main conduction mechanism. The full diode parameters were extracted from reverse and forward current–voltage characteristic. The extracted parameters were barrier height ~ 0.54 eV, series resistance of 660 Ω, and an ideality factor of 5.6.

The development of silicon-based sensor devices has enabled the possibility to pursue novel integrated smart sensor technologies. Under this scenario, capacitive sensor devices are one viable option for implementing different kinds of applications. In this paper, an interdigitated coplanar capacitive device fabricated over a silicon substrate is presented and its potential use as liquid sensor is demonstrated. Additionally, a detailed capacitance model, which includes the parasitic capacitances introduced by the silicon substrate, was developed. The capacitance model has been theoretically validated through finite-element simulations as well as experimentally by comparison with fabricated devices. A polydimethylsiloxane mold has been fabricated and bonded to the sensor device with the aim of defining a cavity to collect the liquid sample into the device’s active region. The active capacitance component correlates to the electric field coupling between adjacent metal lines. Therefore, any change to the dielectric constant of the medium above the coplanar metal lines will produce a change to the device capacitance. Finally, the main guidelines for device performance improvement are depicted.

In this article, we present the analysis of the nonlinear harmonic distortion (HD) characteristics for two kinds of amorphous oxide semiconductor thin film transistors (AOSTFTs) based on SiO2/indium–gallium–zinc oxide (IGZO) and HfO2/hafnium–indium–zinc oxide (HIZO), applying the integral function method (IFM). An analysis of the distortion of the transistors used as quasi-linear resistor and the variation in HD as a function of the parameter ${g}_{m}/{I}_{\text {DS}}$ are also included. As far as we know, this kind of study has not been reported before. It is shown that parameter HD2 does not present a minimum as in MOSFETs, because the transfer characteristic does not present an inflection point. The value of HD2 is higher than that of HD3 in the whole operating ranges. When the transistor is used as quasi-linear resistor for different ${V}_{G}$ bias, HD2 is greater than HD3 in more than 50 dB. Because HD2 is significantly greater than HD3, the total HD (THD) parameter can be considered practically equal to HD2. In addition, the behavior of HD around the low-power operating region is shown.

TiO2 films have been used for novel sensor devices, thanks to their optical and chemical properties. The development of those applications often requires the features of rectifier devices. In this scenario, TiO2-based Schottky diodes become an interesting alternative. In this letter, a detailed electrical characterization of TiO2-based Schottky diodes is performed. Thin films of the three crystalline phases have been obtained by the inkjet printing technique at room temperature. Thermionic and Poole–Frenkel emission are identified as the main conduction mechanisms in these devices, and the barrier heights are reported for each crystal phase.

In recent years, inkjet printing has been found to be a very promising and useful method for material deposition, and even semiconductor films can be deposited directly from a colloidal dispersion (ink) onto a large variety of substrates. The ink properties, such as solvodynamic particle size, zeta potential, isoelectric point, jetting performance, wetting and adhesion on substrates, should be optimized in order to achieve uniform deposition. In this work, the preparation of very stable colloidal dispersions based on TiO2 in three different crystal phases is presented. TiO2 has received a lot of attention because of its potential application in electronic devices. TiO2 inks were characterized by dynamic light scattering (DLS) measurements and the results show that the average solvodynamic particle size is around 25, 32 and 28 nm for anatase, rutile and brookite, respectively. The films obtained by inkjet printing were characterized by X-ray diffraction analysis, scanning electron microscopy, and UV–Vis spectrophotometry. The results show that the inkjet printed films were uniform, with thicknesses of 70, 140 and 130 nm for anatase, rutile and brookite, respectively. The current-voltage characteristics of conducting oxide-TiO2-Ag devices show diode behavior, confirming the semiconductor nature of the TiO2 films prepared by the inkjet printing technique. The ink preparation procedure reported in this work allows for the deposition of homogeneous and uniform films of all three phases of TiO2, and their potential for application in electronic devices.

Several basic thin-film transistor (TFT) models have been developed to describe the electrical characteristics of the device, most of them only considering the fundamental instability effects during static mode operation. However, representing the dynamic behavior is also a major concern for circuit design due to the electrical stress changes over time. Under this scenario, empirical models have been previously demonstrated to reproduce the current instability effects under specific conditions, but they do not consider in detail the phenomena taking place when the TFT is under dynamic electrical stress. In this paper, a new semianalytical model is presented to describe the dynamical behavior of the TFT under stress. This model considers the impact of the negative charge trapped at interfacial states as well as the mobility degradation. To validate the model, we compare the results with experimental measurements from our group, (using CdS TFT), and other semiconductor TFTs (a-Si:H, SnO, IZO, and IGZO) reported by other authors.

A crystalline-like temperature dependence of the electrical characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) is reported, in which the drain current reduces as the temperature is increased. This behavior appears for values of drain and gate voltages above which a change in the predominant conduction mechanism occurs. After studying the possible conduction mechanisms, it was determined that, for gate and drain voltages below these values, hopping is the predominant mechanism with the current increasing with temperature, while for values above, the predominant conduction mechanism becomes percolation in the conduction band or band conduction and IDS reduces as the temperature increases. It was determined that this behavior appears, when the effect of trapping is reduced, either by varying the density of states, their characteristic energy or both. Simulations were used to further confirm the causes of the observed behavior.

An exploratory study was conducted to know how the students within the Faculty of Engineering of the Universidad Veracruzana use the electric power provided by the school. A group of them was consulted on the amount of equipment they use during their stay in the classroom. Likewise, a total energy consumption and its economic cost for the electricity bills of the university was calculated. In addition, a comparison of consumption of electrical equipment was made to verify the electrical power used inside the facilities to confirm the information provided by the manufacturer against the measured value of actual shape.

We introduce experimental results of the I-V characteristics degradation of a Silicon SOI technology for RF applications when exposed to both; a 28 GHz and a DC stress input signals. Then we compare the effect of DC and RF stress on threshold voltage and Drain-Induce-Barrier-Lowering reliability. We observe that reliability under RF stress is gate voltage dependent, and in some cases an improvement of the 1-V characteristics is observed. A hypothetical explanation for the degradation/enhancement under RF stress is attributed to self-heating and self-healing (SH2).

In this paper, based on a full intrinsic–extrinsic model for symmetric doped double-gate MOSFET, we analyze the impact of FinFET gate resistance over the inverter and ring oscillator performance. It is shown that, when the total number of fins remains constant, the propagation delay can be improved thanks to the multifinger configuration that translates into the gate resistance reduction. Furthermore, the fin spacing in addition to source/drain fin extension reduction are of primary importance to improve the digital circuit performance.

The impact on the electrical behavior of thin film transistors, TFTs, based on zinc oxide, ZnO-based TFTs, with temperature is analyzed. ZnO is deposited using pulsed laser deposition techniques and the temperature used during the entire fabrication process is kept below 100 °C. Up to 330 K, the transfer curves practically remain constant or slightly shifted toward more positive voltages. For temperatures up to 330 K, they show the combined effect of the threshold voltage shifting toward more negative voltages and the increase of series resistance. The drain current shows an Arrhenius-type dependence with temperature in subthreshold regime with activation energy of around 0.53 eV. In above threshold regime, for temperatures above 330 K, the activation energy is around 0.15 eV.

These last years, the triple-gate fin field-effect transistor FinFET has appeared as attractive candidate to pursue the complementary metal-oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three-dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double-gate metal-oxide-semiconductor field-effect transistor symmetric doped double-gate MOSFET to reproduce the experimental dc and RF behaviors for 40-nm technology node Silicon-on-Insulator triple-gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small-signal behavior, the current gain, and the maximum available power gain cut-off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Copyright © 2014 John Wiley & Sons, Ltd.

Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology Roadmap of Semiconductors projection, it is mandatory to find layout or technological solutions to reduce the total parasitic gate capacitance. In this context, it is necessary to develop a model that describes the parasitic capacitance in terms of the FinFET geometry. In this paper, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3-D numerical simulations, is presented. The model takes into account the external (five components) and internal (two components) fringing capacitances from the gate to the source/drain electrodes as well as the overlap capacitances. Comparisons with experimental results are presented to validate the developed model. Finally, based on the developed model, the evolution of the total parasitic gate capacitance as the channel length is reduced toward the 12-nm technology node is analyzed.

Multiple-gate MOSFETs became an industrial reality in the last years. Due to a pragmatic trade-off between CMOS process baselines compatibility, improved performance compared to planar bulk architecture, and cost, bulk FinFETs emerged as the technological solution to provide downscaling for the 14/22 nm technological nodes. In this work, a charge based DC compact model based on the SDDG Model is demonstrated for this new generation of FinFET transistors and describes continuously the transistor characteristics in all operating regions. Validating the model against two bulk FinFET baselines (NMOS, PMOS, various gate lengths and EOT), an excellent agreement is found for transfer and output characteristics (linear and saturation regimes), transconductance/output conductance, and g m /I DS characteristics. Temperature dependence is also taken into account and validated ( T range from 25 °C up to 175 °C).

Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of CMOS technology, because of their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations, we analyze the impact of the extrinsic gate capacitances on the RF behavior of FinFETs. It is shown that the reduction of the fin spacing, the modification of the fin geometrical aspect ratio (height/width) as well as the optimization of the fin spacing-fin Source/Drain extension ratio can significantly improve the FinFET RF performance.

The development of compact models for double-gate (DG) MOSFETs and FinFETs necessary in circuit simulators is an important research field, which allows the efficient practical characterization of these devices, as well as their application in analog circuit design. In this paper we review and assess different approaches for developing core and complete compact models for DG MOSFETs and FinFETs.

Collagen and elastin are the two most abundant proteins in the human body, and as biomaterials offer fascinating properties to composite materials. More detailed investigations including these biomaterials within reinforced composites are still needed. This report describes physicochemical properties of fibers composed of collagen type I, collagen III, elastin and polycaprolactone (PCL). Prior to the electrospinning process, PCL was functionalized through covalent attachment of -NH2 groups by aminolysis reaction with hexamentilendiamine. The fibers were fabricated by electrospinning technique set up with a non-conventional collector. A morphological comparative study was developed at different rations of collagen type I, observing in some cases two populations of fibers. The diameters and morphology were analyzed by SEM, observing a wide array of nanostructures with diameters of ~310 to 693nm. Chemical characterization was assessed by FT-IR spectroscopy and the functionalized PCL was characterized through ninhydrin assay resulting in 0.36mM NH2/mg fiber. Swelling tests were performed for 24h, obtaining 320% for the majority of the fibers indicating morphological stability and good water uptake. In addition, contact angle analysis demonstrated adequate permeability and differences for each system depending mainly upon the type of biopolymer incorporated and the functionalization of PCL, ranging the values from 108° to 17°. Moreover, differential scanning calorimetry results showed a melting temperature (Tm) of ~60°C. The onset degradation temperatures (Td,onset) ranged between 115 and 148°C, and were obtained by thermogravimetric analysis. The local mechanical properties of individual fibers were quantified by atomic force acoustic microscopy. These results propose that the physicochemical and mechanical properties of these scaffolds offer the possibility for enhanced biological activity Thus, they have a great potential as candidate scaffolds in tissue engineering applications.

The electrical performance of RF magnetron sputtered Hafnium-Indium-Zinc-Oxide-based thin film transistors (HIZO TFTs) is compared using two different gate dielectrics: a) RF sputtered HfO 2 and b) thermally grown SiO 2 . For HfO 2 devices, output characteristics showed higher drain-currents capabilities with a reduction of the TFT operation voltage range from 0–15 V, when using SiO 2 , to 0–8 V. The HfO 2 dielectric constant was around 15, measured at 1 kHz. Vt was less than 2 V for HfO 2 devices and around 5 V for SiO 2 devices.

With the downscaling of MOSFETs the relative importance of access resistances on transistor behavior and thus on integrated circuits performance significantly increases. Several DC and Radio Frequency characterization techniques have been proposed in the literature to extract the access resistances. It has been demonstrated that the mobility degradation with the vertical electric field in advanced MOSFETs and the transistor asymmetry might strongly degrade the accuracy of the extracted resistance values. Based on simulation and experimental results, correction factors are proposed and guidelines are drawn to help the user for choosing the right extrinsic resistance extraction methodology depending on a few figures of merit associated to the measured data of the FET device. Based on our conclusions, a robust characterization method for deep-submicron devices is proposed and successfully applied to FinFETs.

The post-breakdown leakage current in electrically stressed metal-oxide-semiconductor structures with thin stacked layers of titanium dioxide (TiO2) over silicon dioxide (SiO2) Was investigated. The samples were obtained by plasma oxidation at room temperature. Multiple dielectric breakdowns were induced by the application of successive high-field voltage ramps. The resulting current-voltage characteristics were simulated using an equivalent electrical circuit model consisting in a diode with series and parallel resistances, which is solved using the Lambert W function. We show that after the first breakdown event the current that flows through the non-damaged gate stack area may still play a major role in determining the shape of the post-breakdown current-voltage characteristic. Similarities and differences with previous studied systems are discussed. (C) 2008 Elsevier B.V. All rights reserved.

The dependence with the measurement frequency observed in the Capacitance-Voltage characteristics of Metal-Insulator-Semiconductor structures using an amorphous oxide semiconductor material is presented and analyzed. It is demonstrated by simulation that the effect is due to the Distribution of States (DOS) present in the energy gap of the semiconductor material and strongly depends on the capture cross section of the DOS.

The microelectronics industry has progressed astonishingly along several decades, thanks to the MOS transistor shrinkage. However, the parasitic gate capacitance becomes an important concern for device behavior optimization in the nanometric range. The fringing parasitic gate capacitance exhibits weaker channel length dependence than the intrinsic counterpart. For this reason, the relative weight of the parasitic gate capacitance will be more significant for future technology nodes. In this contribution, an extraction procedure to determine the main fringing components of a simple MOS structure is presented. Numerical simulations were used to validate the presented methodology. Finally, results indicate that for sub-25 nm gate electrode length, normalized total fringing capacitance associated to the transistor width is greater than the intrinsic counterpart.

The electrical properties of RF magnetron sputtered HfO 2 layers as dielectric and Hafnium-Indium-Zinc-Oxide HIZO as semiconductor in metal-insulator-semiconductor (MIS) structures are investigated. The dielectric constant of the HfO 2 layer was around 9 measured at 10 kHz. The critical electric field was higher than 5×105 V/cm and the leakage current below 5×10−9 A/cm2. The effective charged density of interface states in the order of 5×1012 cm−2. Flat band shift due to polarization of the dielectric at voltage rage between −5 and 5 V is below 0.5 V. The RF deposited HIZO layer presents higher density of interface and bulk traps than similar layers deposited by other more complex techniques requiring higher processing temperature. However, results indicate that they can still be used in low voltage range amorphous oxide semiconductor thin film transistors AOSTFTs.

In this paper we present basic features and oxidation law of the room temperature plasma oxidation, (RTPO), as a new process for preparation of less than 2 nm thick layers of SiO2, and high-k layers of TiO2. We show that oxidation rate follows a potential law dependence on oxidation time. The proportionality constant is function of pressure, plasma power, reagent gas and plasma density, while the exponent depends only on the reactive gas. These parameters are related to the physical phenomena occurring inside the plasma, during oxidation. Metal-Oxide-Semiconductor (MOS) capacitors fabricated with these layers are characterized by capacitance–voltage, current–voltage and current–voltage–temperature measurements. Less than 2.5 nm SiO2 layers with surface roughness similar to thermal oxide films, surface state density below 3 � 10 11 cm � 2 and current density in the expected range for each corresponding thickness, were obtained by RTPO in a parallel-plate reactor, at 180 mW/cm 2 and pressure range between 9.33 and 66.5 Pa (0.07 and 0.5 Torr) using O2 and N2O as reactive gases. MOS capacitors with TiO2 layers formed by RTPO of sputtered Ti layers are also characterized. Finally, MOS capacitors with stacked layers of TiO2 over SiO2, both layers obtained by RTPO, were prepared and evaluated to determine the feasibility of the use of TiO2 as a candidate for next technology nodes. D 2005 Elsevier B.V. All rights reserved.

Scaling rules for sub-micrometric MOS devices have led to the necessity of ultrathin dielectric films and high- k dielectric layers. In this paper we present first results of room temperature plasma oxidation to obtain ultrathin layers of SiO 2 and TiO 2 . The oxidation process in O 2 and N 2 O shows a power law dependence with time and inverse proportionality with pressure. The oxidation rate is inversely proportional to pressure for both high and medium resistivities substrates. An oxidation model is proposed to explain this behavior. Ellipsometric and C – V characterization show complete oxidation of titanium verifying that a dielectric layer is formed.

In this paper, a semi-analytical extrinsic gate capacitance model for Triple Gate FinFET, based on three-dimensional numerical simulations, is presented. The model takes into account the source/drain electrode and contact areas. It includes 5 capacitance components that describe the different fringing electrical couplings that exist inside the FinFET structure. The semi-analytical model accurately calculates the total extrinsic gate capacitance as function of the main geometrical parameters of Triple-Gate FinFET.

A methodology to properly establish an accurate SOI FinFET compact model through SPICE simulator is presented. This compact model is implemented in Verilog-A to simulate the performance of RF circuits based on SOI FinFET technology. It predicts well static behavior of the transistor and circuit, as well as their small-signal RF behavior by modeling the intrinsic capacitances and also the effects of the gate resistance and the extrinsic gate capacitances. Finally, the comparison between the simulated and measured performance of a Low Noise Amplifier demonstrates the validity and the capabilities of this compact model to simulate the dc and RF behavior of RF circuits.

CMOS technology has been guided by the continuous reduction of MOS transistors used to fabricate integrated circuits. Additionally, the use of high-k dielectrics as well as a metal gate electrode have promoted the development of nanometric MOS transistors. Under this scenario, the proper modelling of the gate capacitance, with the aim of adequately evaluating the dielectric film thickness, becomes challenging for nanometric metal-insulator-semiconductor (MIS) structures due to the presence of extrinsic fringing capacitance components which affect the total gate capacitance. In this contribution, a complete intrinsic–extrinsic model for gate capacitance under accumulation of an MIS structure, together with an extraction procedure in order to independently determine the different capacitance components, is presented. ATLAS finite element simulation has been used to validate the proposed methodology.

In this paper, we develop an analytical model to simulate strained silicon NMOSFETs, which allows to describe the drain current. Numerical simulations were performed in order to validate the model, where different technological parameters were considered (e.g. impurity concentrations in Si 1−y Ge y and strained-silicon films). A good agreement with numerical simulations has been obtained.

Modeling of the small-signal equivalent circuit of SOI FinFETs through SPICE simulations is presented. A compact model implemented in Verilog-A predicts well the DC characteristics of RF SOI FinFETs and allows the extraction of the intrinsic conductance, transconductance and capacitances at any selected operating point. The intrinsic small-signal equivalent circuit composed of those extracted lumped elements is used in SPICE simulator. This paper compares the parameters extracted from both DC and wideband S-parameter methods.

Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations we analyze the impact of the extrinsic gate capacitance on the RF behavior of FinFETs. It observes that the extrinsic capacitances are larger than the intrinsic counterparts for sub-100 nm devices. Furthermore, the reduction of the fin spacing as well as the increase of the fin geometrical aspect ratio (height/width) can improve significantly the FinFETs RF behavior.

In the last years the MOS transistor technology has reach very high cut-off frequencies (near to 500 GHz), thanks to the continuous reduction of the channel length, but the short-channel-effects (SCE) strongly affects the MOSFET behavior below 60 nm. For such technology nodes the Multiple-Gate transistor (MuGFET) appears as a promising alternative to continue with the International Technology Roadmap of Semicoductors (ITRS) projections. In this paper, limitations and possible improvements of MuGFETs are presented.

In the last few years, many efforts have been made looking for the improvement of the DC and RF performance of MOS transistors. In this scope, Schottky-Barrier transistors appear as very interesting alternative to conventional devices. In this paper we present the non-linear behavior of dopant segregated n-type SB-MOSFETs with 180 nm channel length.

The communication industry has always been a very challenging and profitable market for semiconductor companies. The new communication systems are today very demanding; they require high frequency, high degree of integration, multi-standards, low power consumption, and they have to present good performance under harsh environment. The integration and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. The bottleneck for further advancement is the analog front-end. Present-day transceivers often consist of a three or four chip-set solution combined with several external components. A reduction of the external components is essential to obtain a lower cost, power consumption and weight, but it will lead to a fundamental change in the design of analog front-end architectures. The analog front-end requires a high performance technology, like GaAs or silicon bipolar transistors, with devices that can easily achieve operating frequencies in the GHz range. For a digital signal processor, a small device feature size is essential for the implementation of complex algorithms. Therefore, it appears that only the best submicron CMOS technology is suitable for a feasible and cost-effective integration of the communication systems. This last decade MOS transistors have reached amazingly high operation speed and the semiconductor community has noticed the Radio Frequency possibilities of such mainstream devices. Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency reaching cutoff frequencies close to 500 GHz for nMOSFETs and for harsh environment (high temperature, radiations) commercial applications. From its early development phase till recent years, SOI has grown from a mere scientific curiosity into a mature technology. Partially Depleted (PD) SOI is now massively serving the 45-nm digital market where it is seen as a low cost low power alternative to bulk silicon. Fully depleted (FD) devices are also widely spread as they outperform existing semiconductor technologies for extremely low power analog applications. 9

A new extraction method of the intrinsic parameters of the small-signal equivalent circuit model of SOI MOS transistors (MOSFET) is presented. This new method does not need the previous knowledge of the extrinsic series resistances, moreover, it is possible to directly determine the intrinsic parameters at the bias point of interest. Floating-Body SOI MOSFETs are analyzed using this method.

A compact model for small-signal equivalent circuit of DG-MOSFETs is presented. The intrinsic parameters are obtained from DC analytic compact model. This DC model allows determining the mobile charge inside the transistor channel, from which the intrinsic parameters are derived. Additionally, the extrinsic capacitances are calculated and included into the model. This compact small-signal model allows determining the transistor RF behavior at different bias conditions and for different technological parameters in a more simple and precise way.

Adequate modelling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We present the relative sensitivity of each published RF characterization method to the measurement noise floor of Vectorial Network Analyzer. Additionally, the Bracale's method demonstrates to be less sensitive to the measurement noise but the extracted resistance values suffer from the mobility degradation due to the transversal electric field and the asymmetry of the device under test. Based on these theoretical and experimental results we propose a revised extraction procedure suitable for deep submicron transistors.

Adequate modeling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We demonstrate that all published RF characterization methods properly work to extract the extrinsic series resistances when the RF measurement noise is not considered. However, when Vectorial Network Analyzer (VNA) measurement noise on S-parameters is included in the simulations, we clearly conclude that the extracted series resistances are dependent on the extraction procedure. These results demonstrate the high sensitivity of the extracted RF MOSFETs small-signal equivalent circuit with S-parameters measurement noise and therefore the need of specific filtering methods to reduce the VNA noise floor.

This work presents the high-temperature DC and RFbehaviorsofpartially-depletedSOI MOSFETs. DC and RF figures of merit are deeply investigated, both analytically and experimentally, to provide a complete study ofhigh-temperature performance and a comparison between floating-body and body-tied transistors. A highly stable RF performance is noticed especially for cutoff frequency and intrinsic elements for temperature as high as 250° C.