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International audience

A new concept for improving efficiency of a charge pump system is presented. The concept is based on a set of elementary charge pumps connected in parallel in addition to the detection of the number of memory cells to be programmed at the same time. The proposed solution is able to supply current to a memory cell, while operating with maximum efficiency by activating one, two or more charge pumps. The proposed system is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. In the worst case where only one cell is to be programmed, simulation results show an improvement of power efficiency by a factor 2. The area penalty of the proposed system is only 3.8%.

An ultra-low power regulated charge pump system based on charge recycling between a tank capacitor and the charge pump output load capacitor is presented. The proposed circuit is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. Simulation results show a maximum current reduction of about 38% compared to a conventional regulated charge pump system. Rise time until the steady state is reached is also reduced by 17%.

An ultra-low power and high performance voltage-mode sense amplifier is presented. Based on charge recycling between a tank capacitor and the bit line parasitic capacitor, a reference voltage is created dynamically and the memory precharge step starts from half the supply voltage. The precharge and word line activation are independent, avoiding the extra consumption due to the direct path between power supply and ground during precharge. The proposed circuit is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. Simulation results show a read access time of about 20.6 ns and an average power consumption of 0.56 µW/MHz/bit in typical operating conditions at 27 °C.

8th IEEE International Memory Workshop (IMW), Paris, FRANCE, MAY 15-18, 2016; International audience; a new approach for improving the power efficiency of the conventional four-phase charge pump is presented. Based on the multi-step capacitor charging and the charge sharing concept, the charge pump design is able to reduce the overall power consumption by 35% compared to the conventional four-phase charge pump and by 15% compared to a charge sharing charge pump, for an output current of 200 mu A with 12V output voltage.