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In the present era, there is tremendous need for digitization of medical data, which are collected from animals and human beings, etc. For this purpose, the collected samples are converted into digital format for proper analog-to-digital converters (ADCs). After the required preprocessing, these can be used, and for analysis, these data are again converted back into readable format using suitable digital-to-analog converters (DACs). In medical electronics, suitable sensors are used for data acquisition, and much attention is directed toward biomedical sensors integrated with a suitable data converter architecture. These integrated medical tools (or systems) are generally used for online diagnosis and monitoring without incurring heavy expenditure. This chapter will give brief emphasis on the coding and quantizing, data converter parameters, ADC and DAC architecture, and a few applications of ADC and DAC in biomedical. In this chapter, there are sections: Section 1 gives a brief introduction to ADC, Section 2 gives an overview of different functions used in ADC like sampling, encoder, etc., Section 3 briefly describes different ADC and DAC parameters, Section 4 describes ADC and DAC architecture, Section 5 describes an application of ADC for biomedical, and Section 6 is the conclusion.

Purpose The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model. Design/methodology/approach The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy. Findings The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. Ion/Iambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs. Originality/value The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

To support miniaturization and low power demands of the electronic systems market, the essential scaling laws are marred due to performance degradation by Short Channel Effects. The recently developed TFETs follow interband tunneling (BTBT) as their current injection mechanism and have better subthreshold swing (below 60mV/dec) compared to the conventional SOI MOSFETs. This article presents an analytical model for drain current in the super threshold region. The parabolic potential approach is used including the effect of fringing fields and mobile charges in the channel. This model predicts the surface potential, electric field and BTBT current with reasonable accuracy, thus reflecting most of the physical device phenomena.

The plant that have therapeutic actions or wield beneficial pharmacological outcomes on animal bodies are usually assigned...

This paper presents an in depth study and analysis which shows that the Double gate MOSFET has emerged as one of the most favorable devices due to short channel effect immunity, off-current reduction ability and more scaling possibility. The devices with less than 0.1 μm gate length can maintain near ideal subthreshold factor. This paper also presents some new modifications in the existing devices, in order to keep up with the performance improvements, such as Asymmetric Undoped Double gate MOSFET, Symmetric and Asymmetric Underlap Double gate MOSFET, high K TMDG MOSFET, high K Spacer Asymmetric Underlap Double gate MOSFET, Graded Channel Double gate MOSFET and Dual-insulator Double gate MOSFET.

The main idea dominating the current trends in VLSI circuits is to offer large scale integration coupled with extensive power reduction solutions, even with newer devices and topologies[1]-[2]. However the significant increase in the gate switching energy results in higher power dissipation and costly heat sinks. At that point, to constrain the dissipation of power, elective arrangements at various level of deliberation are suggested. The power dissipation is significantly reduced by the adiabatic logic structure at the expense of circuit complexity to accomplish low power dissipation, switching procedures are used. Adiabatic logic discussed here provides an approach to use the energy repeatedly that is put away in the load capacitors. This paper briefs some of the adiabatic logic families such as PFAL and SAL. It aims at comparing the effectiveness of adiabatic logic with respect to power dissipation and delay. The implementation of the 4 bit CLA validates the credibility of the logic. A graph has been plotted to show the effect of temperature on sub threshold adiabatic logic based 4 bit CLA. The simulation results obtained from the vituoso environment of cadence tool suggests three folds power reduction in the ECRL topology as compared to the other existing topology.

The CZTSSe is the modified version of CZTS with selenium infusion. It shows maximum efficiency in the band gap from 1 to 1.4 eV. In our present work CZTSSe based solar cell is investigated using Wx-Amps tool. The Mo layer, absorber layer, CdS layer, i-ZnO [4]and Al-ZnO layers with their electrical, optical and material parameters are fitted in the tool. The vital parameters such as carrier density, thickness of the CZTSSe absorber layer, operating temperature, CdS buffer layer thickness and its carrier density on the cell interpretation are calculated. From[4] the simulation results it is apparent that the optimal absorber layer varies from 2.9 µm to 3.7 µm. The temperature variation has a strong influence on the efficiency of the cell. An optimal efficiency of 22% (With Jsc=33 mA/cm2, Voc=0.98 V, and fill factor= 68%) are attained. These results will give some insight for makeing higher efficiency CZTSSe based solar cell.

Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in today's technological environment. The continuous scaling of CMOS technology significantly limits the performance of 6T SRAM cell in terms of leakage power and stability. With remote chances to further improve the MOSFET technology in future, Carbon Nanotube Field Effect Transistors (CNTFETs) are being widely studied as the possible alternatives. In this paper, the conventional 6T SRAM cell is compared with CNTFET based SRAM cell. The conventional 6T SRAM cell is designed using Cadence Virtuoso Tool in 180nm and 45nm Technology. The Verilog-A code of CNTFET for replacing nMOS and pMOS are separately simulated in Cadence Virtuoso Tool. The CNTFET based SRAM cell is technology independent. The performances are evaluated in terms of leakage power, delay and stability to show that the CNTFET based SRAM cell can successfully replace the CMOS based SRAM cell.