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Keyword spotting (KWS) has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always on nature and the variety of speech, it necessitates a low-power design as well as user customization. This article describes a low-power, energy-efficient KWS accelerator with static random access memory (SRAM)-based in-memory computing (IMC) and on-chip learning for user customization. However, IMC is constrained by macro size, limited precision, and nonideal effects. To address the issues mentioned above, this article proposes bias compensation and fine-tuning using an IMC-aware model design. Furthermore, because learning with low-precision edge devices results in zero error and gradient values due to quantization, this article proposes error scaling and small gradient accumulation to achieve the same accuracy as ideal model training. The simulation results show that with user customization, we can recover the accuracy loss from 51.08% to 89.76% with compensation and fine-tuning and further improve to 96.71% with customization. The chip implementation can successfully run the model with only 14 $\mu \text{J}$ per decision. When compared to the state-of-the-art works, the presented design has higher energy efficiency with additional on-chip model customization capabilities for higher accuracy. [ABSTRACT FROM AUTHOR]

This investigation proposes a novel dc-balanced low-jitter transmission code, a 4-PAM symmetric code, for a 4-PAM signaling system. The 4-PAM symmetric code preserves all of the useful characteristics of the 8B/10B code such as dc-balanced serial data and guaranteed transitions in the symbol stream for clock recovery. Moreover, the proposed method decreases the jitter of the timing transition of the data in the receiver and consumes half of the data bandwidth, because it transmits in 4-PAM. The design results using the UMC 0.18-[micro]m process demonstrate that the new transmission code can decrease the jitter of the transition point by [+ or -] 25% of the transition region. The operation speed of the encoder/decoder for the 4-PAM symmetric code is 819 MHz with 16-b inputs (13.1 Gb/s) and 704 MHz with 16-b outputs (11.3 Gb/s). Index Terms--Low jitter, 4-PAM, transmission code, 8B/10B code.

In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scrambler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-[micro]m CMOS process. Index Terms--Parallel scrambler, register, XOR.

A low-error reduced-width Booth multiplier using a proper compensation vector is proposed. The compensation vector is dependent on the input data. The compensation value will thus be adaptively adjusted when the input data are different. Design results from a 16X16 to 16 Booth multiplier show that the gate counts and critical path delay of the new reduced-width multipliers is 50.94% and 66.04% of the post-truncation reduced-width multiplier. A module generator of our proposed architecture is developed, that will generate C code and Verilog code for each reduced-width multiplier. Pulse-shaping filter-system applications used in CATV transceivers show promising performance with 50.04% hardware reduction and 33.82% reduction in the critical path delay. Index Terms--Compensation vector, digital signal-processing (DSP) application, reduced-width Booth multiplier.

In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-IF oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. The design example shows that it consumes only 24% power of direct implementation while occupying 26% less area. Index Terms - Frequency down converter, low power, multirate architecture.

An on-chip differential-amplifier-based dc-to-dc voltage down converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator and high current drive capability. VDC converts 5 V to lower voltage so that the internal circuits of the chip are used. In this paper, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA) and temperature dependency of 3.2 mV/[degrees] C. The VDC chip was fabricated in a 0.8-[[micro]meter] single-poly-double-metal CMOS process and layout size is 690*210 [[[micro]meter].sup.2]. The output voltage is stabilized within [+ or -]2.8% for supply voltage with [+ or -]10% variation achieved. Index Terms - DC-to-DC, low-power digital system, voltage down converter.