Search

The transient dual interface method (TDIM), proposed by the JEDEC 51-14 standard [1] , determines the junction-to-case thermal resistance of power electronics with the separate point of two transient thermal impedance curves under different contact conditions. However, the influence of the junction temperature is not considered and this underestimates the actual value with earlier separation point. This phenomenon is presented first with experimental results at different junction temperatures. Electro-thermal finite element simulations and simulation with semiconductor physical behavior in the devices simulations are performed to explain the root reason. After that, the improved TDIM with the junction temperature compensation is proposed to improve the accuracy. The experimental results show that the improved TDIM improves the accuracy of about 9.5% for 600-V discrete IGBT devices.

The lifetime evaluation is strongly influenced by the measurement accuracy of the junction temperature with the V ce(T) method during power cycling test (PCT). However, the measurement delay time t md, the time between which the load current is switched off and the test pulse is applied, induces a maximum junction-temperature offset Δ Tjm . The JEDEC [1] suggested square root t method is found only to be suitable for devices with surface-close heat generation and will induce errors for other devices such as IGBTs. In this article, two novel methods, the simulated Δ Zth and the Cauer thermal model, are proposed. The principle and accuracy of these two methods are discussed in detail. Furthermore, the measured Zth curve, or the Foster thermal model method, is proven not suitable for the correction of the maximum junction-temperature offset, as it will induce the same error as the square root t method.

In this article, the influence of the insulated gate bipolar transistor (IGBT) chip-near temperature gradient on the failure modes in the power cycling test is investigated with the finite element (FE) simulation and experiment. Two important aspects influencing the temperature gradient are studied: one is the load current pulse duration $t_{\mathrm {on}}$ from the testing aspect; the other is the area ratio between the chip region and direct copper bonding (DCB) top side copper determined by the device package layout. The IGBT chip-near temperature gradient caused by these two factors is first investigated using the FE thermal simulation. It was found that by varying $t_{\mathrm {on}}$ and the area ratio, a significant influence on the temperature gradient of the chip and the average temperature of the solder layer can be achieved, which could lead to different dominating failure modes under the same power cycling test conditions. Furthermore, experiments considering those two factors were designed and performed to verify the inference derived from the simulation. The results show that the failure mode indeed can be shifted because of the changed temperature gradient.

In this article, the influence of the gate drive unit on the short-circuit (SC) type II and III behavior of insulated gate bipolar transistor (IGBT) modules was investigated in detail. It is found that the real gate voltage of the IGBT chip contacts cannot be measured across the auxiliary pins of a power module. The difference between applied gate voltage at the sense contacts and the real gate voltage at the IGBT gate contact is shown to be highly dependent on the common-source inductance and hence, the packaging concept. The value of the gate resistance has a significant effect on SC behavior. A gate voltage self-clamping effect during SC was found and verified with the help of circuit simulation. Finally, a gate voltage clamping circuit for improved SC ruggedness of the IGBT modules is introduced. Based on the clamping circuit, a new fast SC type II and III detection method is developed and tested, which can detect and turn- off the SC event within 400 ns.

This work investigates modification on the top-side aluminium (Al) metallisation of 1.2 kV insulated-gate bipolar transistors (IGBTs) under repetitive short-circuit (SC) type-I measurements for two different parasitic inductances of 45 and 380 nH. The presence of current-density filaments starting at the collector side during SC leads to local temperature increase of the emitter metallisation and thus to modification of the top Al surface in the pattern of the current filaments. Here, two techniques thermo-reflectance microscopy, which can detect the surface temperature during repetitive short circuits directly and Al modifications after repetitive SC with analysis under optical microscope after the test have been considered. At 45 nH, with different DC-link voltages from 300 to 600 V, the Al modification pattern is non-uniform and it becomes uniform for V DC >600 V. However, for 380 nH parasitic inductance and for DC-link voltages 300 and 400 V, the Al reconstruction shows a non-uniform pattern and becomes uniform for V DC ≥500 V. The SC simulations were performed by using a simplified front-side IGBT structure using variable DC-link voltages and inductances to reproduce the filament behaviour.

In this paper, several power cycling tests under single or combined test conditions were undertaken to investigate the applicability of linear cumulative damage theory in the lifetime prediction of power semiconductor devices. The validity of this theory was verified by an experimental method for one lifetime limit, which is an increase of forward voltage at load current by 5%. The corresponding failure mechanism is the degradation of bond wire contacts.

Determination of chip temperature is a key element in the lifetime estimation of power devices. There are several temperature sensitive electrical parameters for this purpose, which allow accurate measuring of the chip temperature on fully packaged devices. Among all these parameters, the forward voltage of a p-n junction is probably the most widely used parameter for temperature determination of a power semiconductor device. In metal-oxide-semiconductor (MOS) gated power semiconductor devices, gate threshold voltage is an alternative parameter with high temperature resolution. In this paper, the p-n-junction forward voltage and the gate threshold voltage of MOS-gated power devices were investigated. The difference between temperature measurements via the two methods was analyzed.

The need for higher switching frequencies, higher operation temperatures and lower volume of power devices increases remarkably due to the increased demand of products with higher power densities, lower weight and smoother power output [1], [2]. Especially, wide band gap materials are needed to fulfill all requirements, but cannot reach their full potential with state of the art planar package technology [1]. To obtain reduced parasitics within the power loop, to reduce the devices footprint, improve heat removal and ensure package reliability, a three dimensional integration of power devices can be utilized [3], [4], [5], [6], [7]. The potential of 3D integration is enormous and essential in order to push power electronic devices to their theoretical limit. Recent developments could not only obtain improved switching proficiencies [8], in addition, remarkable exceedance of active power cycling lifetime and an increased capability to withstand critical overload conditions could be realized [2]. Finally, the establishment of advanced package technologies relies on several reliability and robustness tests. New power module designs are evaluated.

In this paper the gate oxide reliability of SiC MOSFETs has been tested under different stress conditions. Discrete devices of the 1.2 kV class with planar and trench MOS-structure have been examined under positive and negative stair-shaped increased gate bias until the time dependent dielectric breakdown (TDDB). This test procedure was developed to expose extrinsic failures in high temperature gate bias tests. Additionally, three prototype power modules equipped with 6.5 kV SiC MOSFETs have been tested under positive, negative constant voltage gate bias and positive stair-shaped increased gate bias. The threshold voltage together with the output characteristic has been recorded before test start and after every stress period. A significant impact from the V GS(Th) -drift on the output characteristic is shown. Hence, it is recommended to consider the TDDB and the V GS(Th) -drift for lifetime predictions.

Bipolar degradation continues to be a key issue that should be taken into account in 4H-SiC devices using bipolar operation modes. The generation and expansion of recombination-induced stacking faults (SFs) in 4H-SiC devices results in a forward-voltage drift, which has been widely discussed in the literature. In this work, 1.2 kV SiC MOSFET body diodes were stressed at different current densities to investigate the influence of crystal-induced voltage drifts like bipolar degradation caused by stacking faults (SFs), expansion from pre-existing basal plane dislocations (BPDs) or conversion points. Additionally, thermomechanical failures (gate-oxide damage, front-side metallization degradation, bond-wire heel crack and lift-off) inevitably occurred due to high surge-current stress. The measurement results illustrate the spectrum of degradation by applying different current densities to the body diode of SiC MOSFETs.

Various papers in power electronics contain a part of lifetime estimation depending on power cycles in application. The used model is often the CIPS08 lifetime model published at the conference CIPS 2008. In many applications, a lot of cycles with low temperature swings occur. The used model, however, is only valid for temperature swings above 40 K. For temperature swings < 30 K, there are strong deviations, since some materials are now approaching the elastic region. First experimental power cycling results are gained below 30 K temperature swing. Also an approximation for the reliability of low temperature swing is given in this paper.

New results of 1.7 kV and 6.5 kV single chip IGBTs under repetitive SC events are presented and compared with the results of 1.2 kV IGBTs. An observed current filament pattern as well as the filament lateral distance in 1.7 kV IGBTs are compared with the results of 1.2 kV IGBTs. Device simulation was performed by designing 2D as well as 3D IGBT structures to explain the trend of the filament lateral distance as a function of different voltage class. The current filament pattern produced with the help of 3D simulation was compared with the observed current filaments from experimental results. Possible reasons for the mismatch between measurement and 3D-simulation results are discussed.

In this paper, the measurement error caused by the square root t method applied to IGBT devices during power cycling tests is analyzed in detail by the finite element simulation. The influence of power density, voltage class and chip active area on this error is discussed in depth. The simulation results show that it highly depends on the power density, and the square root t method under/over-estimating of the actual value is related to the voltage class rather than to the active area. This error looks acceptable with a power density lower than 300 W/cm2 but rises linearly with high power density and cannot be ignored, especially for transfer-molded devices. It has to be considered in the power cycling tests with high power density.

In this work, thermomechanical failures during single and repetitive surge current events of 40 mΩ class, 1.2 kV SiC MOSFET inverse diodes were investigated. The single event surge current was performed under different pulse length in channel-off mode. It was observed that the body diode survived 10 ms surge currents more than 11 times the application-near nominal current of 20 A. After surge current destruction a failure analysis was performed. At a high surge current event (232 A) the device failed due to the very high temperature, the aluminium metallization was melted around the bond foot and the melted metallization shorted gate and source (GS) metal. In addition to that, repetitive surge current tests, high temperature reverse bias (HTRB) tests under negative gate bias and high temperature gate bias test (HTGB) with samples exposed to repetitive surge current were performed to investigate different aging mechanisms to determine reliability aspects of the inverse diode in SiC MOSFETs.

When silicon carbide power devices are subjected to power cycling tests, specific aspects must be considered for the evaluation of test results in order to investigate aging mechanisms of the packaging technology. A threshold voltage drift as well as bipolar degradation can influence the results depending on the test procedure, while a higher probability of bipolar degradation is given, especially for high-voltage devices. In this paper, four 6.5 kV modules with standard packaging technology have been investigated with two different test procedures in power cycling tests.

This paper presents a gate-voltage clamping circuit based on the negative feedback using the emitter stray inductance of discrete IGBT devices, to improve the Short Circuit (SC) ruggedness of type II and type III, which is more likely to occur in the real applications than SC type I. Specifically, during SC II and SC III, the high short circuit current $I_{\mathrm{SC}}$ increasing rate $di_{sc} / dt$ introduces an inductive voltage, which can be used to suppress the gate voltage overshoot at the beginning of the short circuit, thereby the short circuit current maximum can be reduced. Without short circuit current peak at the initial phase of the SC pulse, the energy of suppressed SC II and SC III is similar to SC type I of the same SC pulse length. The adjustable negative feedback can be achieved with a voltage divider as well.

Typically, power modules are mounted directly on a heat sink and either air or water cooled, therefore the main heat dissipation path is via the baseplate. New semiconductor materials are emerging which allow higher blocking voltages and thus make the housing assembly to a greater challenge. For these reasons, the idea of direct oil cooling and thus the replacement of silicone encapsulation is taken up again. A comparison between oil cooling and water cooling at measurement of the thermal impedance Z th is presented.

There is an increasing demand for high power high voltage diodes. The requirements are for low losses and rugged performance during even under the fastest switching conditions. This paper describes a detailed investigation to optimize the reverse recovery behavior of 4.5 kV Press-Pack diodes under different current commutation slopes up to $15\ \text{kA}/\mu \mathrm{s}$ . Controlled axial lifetime and appropriate field stop (FS) profiles were investigated in order to obtain soft recovery behavior at 10% to 200% of rated current. Phosphorus diffusion and proton implantation were used in order to discover an appropriate process for manufacturing the field stop structure. In addition, the contributions of varied lifetime adjustments at the anode side of the diode have been analyzed and explained using measurements and simulations.