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Sliding-mode control (SMC) is a robust technique used in power electronics (PE) for controlling the behavior of power converters. This paper presents simulations and experimental results of an optimal SMC strategy applied to Semi-Bridgeless Boost Converters (SBBC), which includes Power Factor Correction (PFC). As the main contribution, the optimal coefficients of the SMC strategy are obtained using two metaheuristic approaches, namely the Genetic Algorithm (GA) and Particle Swarm Optimization (PSO). The main objective is to obtain the sliding coefficients that ensure the best converter response in terms of the input current and output voltage, both during start-up and under disturbances (including changes in load, source, and references). The fitness function to be minimized includes two coefficients, namely the Integrative Absolute Error (IAE) and the Integral Time Absolute Error (ITAE), for both the input current and output voltage. These coefficients measure the converter’s effort to follow the control references. The IAE penalizes errors during start-up, whereas the ITAE penalizes errors in the steady state. The tests carried out demonstrated the effectiveness of the GA and PSO techniques in the optimization process; nonetheless, the GA outperformed the PSO approach, providing sliding coefficients that allowed for a reduction in the input current overshoot during start-up of up to 24.15% and a reduction in the setting time of the output voltage of up to 99%. The experimental results were very similar when tuning with the GA and PSO techniques; nevertheless, tuning with the GA technique produced a better response in the face of disturbances compared to the PSO technique.

This paper presents the implementation of an AC three-phase programmable electronic load (PEL) that emulates load profiles and can be used for testing equipment in microgrids (MGs). The implemented PEL topology is built with a voltage source inverter (VSI) which works as a current controlled source and a Buck converter which permits the dissipation of active power excess. The PEL operation modes according to the interchange of active and reactive power and its operation in four quadrants were determined. The power and current limits which establish the control limitations were also obtained. Three control loops were implemented to independently regulate active and reactive power and ensure energy balance in the system. The main contribution of this paper is the presentation a detailed analysis regarding hardware limitations and the operation of the VSI and Buck converter working together. The PEL was implemented for a power of 1.8 kVA. Several experimental results were carried out with inductive, capacitive, and resistive scenarios to validate the proper operation of the PEL. Experimental tests showed the correct behavior of the AC three-phase currents, VSI input voltage, and Buck converter output voltage of the PEL for profile changes, including transient response.

Power Factor Correction (PFC) single-phase AC/DC converters are used in several power electronics applications as full wave control rectifiers improving power quality and providing high standards of efficiency. Many papers dealing with the description or use of such topologies have been published in recent years; however, a review that describes and organizes their specific details has not been reported in the technical literature. Therefore, this paper presents an extensive review of PFC single-phase AC/DC converters operating with the Boost converter topology for low and medium voltage as well as and power appliances. A categorization of bridge, semi-bridgeless, and bridgeless, in accordance with the construction characteristics, was carried out in order to unify the technical terminology. Benefits and disadvantages are described and analyzed in detail. Furthermore, a comparison performance in terms of PFC, Total Harmonic Distortion (THD), power capacity, electromagnetic compatibility (EMC), number of elements, and efficiency is included.

In this paper, a model and solution approach for minimizing internal power losses in Transformers Connected in Parallel (TCP) with tap-changers is proposed. The model is based on power chargeability balance and seeks to keep the load voltage within an admissible range. For achieving this, tap positions are adjusted in such a way that all TCP are set in similar/same power chargeability. The main contribution of this paper is the inclusion of several construction features (rated voltage, rated power, voltage ratio, short-circuit impedance and tap steps) in the minimization of power losses in TCP that are not included in previous works. A Genetic Algorithm (GA) is used for solving the proposed model that is a system of nonlinear equations with discrete decision variables. The GA scans different sets for tap positions with the aim of balancing the power supplied by each transformer to the load. For this purpose, a fitness function is used for minimizing two conditions: The first condition consists on the mismatching between power chargeability for each transformer and a desired chargeability; and the second condition is the mismatching between the nominal load voltage and the load voltage obtained by changing the tap positions. The proposed method is generalized for any given number of TCP and was implemented for three TCP, demonstrating that the power losses are minimized and the load voltage remains within an admissible range.

This paper presents an assessment of capacitor banks and Distribution Static Compensator (D-STATCOM) with respect to their impact on energy quality. Tests were done with capacitor banks built with electrolytic capacitors commonly used in industrial applications and a D-STATCOM. Experimental tests were performed for power factor correction in order to reduce the reactive power demanded from the electrical grid for inductive-resistive loads. For comparative purposes, the control of the D-STATCOM was set to operate with similar compensation conditions to that of the capacitor banks. Results show that under the same test conditions capacitor banks produce higher Total Harmonic Distortion (THD) than D-STATCOM.