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This paper demonstrates how the PIXAPP Photonics Packaging Pilot Line uses its extensive packaging capabilities across its European partner network to design and assemble a highly integrated silicon photonic-based optical transceiver. The processes used are based on PIXAPPs open access packaging design rules or Assembly Design Kit (ADK). The transceiver was designed to have the Tx and Rx elements integrated on to a single silicon photonic chip, together with flipchip control electronics, hybrid laser and micro-optics. The transceiver used the on-chip micro-optics to enable a pluggable fiber connection, avoiding the need to bond optical fibers directly to the photonic chip. Finally, the packaged transceiver module was tested, showing 56 Gb/s loop-back modulation and de-modulation, validating both the transmitter and receiver performance.

Arrayed Waveguide Grating Router (AWGR)-based interconnections for Multi-Socket Server Boards (MSBs) have been identified as a promising solution to replace the electrical interconnects in glueless MSBs towards boosting processing performance. In this article, we present an 8-socket glueless optical flat-topology Wavelength Division Multiplexing (WDM)-based point-to-point (P2P) interconnect pursued within the H2020 ICT project ICT-STREAMS and we report on our latest achievements in the deployment of the constituent silicon (Si)-photonic transmitter and routing building blocks, exploiting experimentally obtained performance metrics for analyzing the 8-socket chip-to-chip (C2C) connectivity in terms of throughput and energy efficiency. We demonstrate an 8-channel WDM Si-photonic microring-based transmitter (Tx) capable of providing 400 (8 x 50) Gb/s non-return-to-zero (NRZ) Tx capacity and an 8 x 8 Coarse-WDM (CWDM) Si-AWGR with verified cyclic data routing capability in O-band. Following an overview of our recently demonstrated crosstalk (XT)-aware wavelength allocation scheme, that enables fully-loaded AWGR-based interconnects even for typical sub-optimal XT values of silicon integrated CWDM AWGRs, we validate the performance of a full-scale 8-socket interconnect architecture through physical layer simulations exploiting experimentally-verified simulation models for the underlying Si-photonic Tx and routing circuits. This analysis reveals a total aggregate capacity of 1.4 Tb/s for an 8-socket interconnect when operating with 25 Gb/s line-rates, which can scale to 2.8 Tb/s at an energy efficiency of just 5.02 pJ/bit by exploiting the experimentally verified building block performance at 50 Gb/s line. This highlights the perspectives for up to 69% energy savings compared to the standard QuickPath Interconnect (QPI) typically employed in electronic glueless MSB interconnects, while scaling the single-hop flat connectivity from 4- to 8-socket interconnection systems.

This paper discusses our progress on high-speed optical transmitters for next generation intra-datacenter interconnects. Silicon integrated photonic systems have a key role to play in this evolution by allowing compact, fast, innovative and cost-effective devices to be manufactured in large volumes. Especially silicon Mach-Zehnder modulators are a very attractive candidate: they are easy to manufacture, easy to use and support both intensity as well as coherent modulation. Key to the next-generation optical transmitter is not only the very high datarates, but also the very small form-factor and low power consumption. This requires leveraging electro-optic co-design of driver electronics and optical modulators.

As next-generation data center optical interconnects aim for 0.8 Tb/s or 1.6 Tb/s, serial rates up to 106 GBd are expected. However doubling the bandwidth of current 53 GBd 4-level pulse-amplitude modulation (PAM-4) transmitters is very challenging, and perhaps unfeasible with compact, non-travelling wave, lumped modulators or lasers. In our previous work, we presented an integrated 4:1 optical serializer with electro-absorption modulators (EAMs) in each path. Transmitter (TX) functionality was shown up to 104 GBd non-return-to-zero (NRZ) On-Off Keying (OOK) or PAM-4. However the performance for PAM-4 was limited by the distortion introduced by the EAM non-linearity. We also presented a real-time, DSP-free 128 Gb/s PAM-4 link with a silicon photonic transmitter using binary driven EAMs in a Mach-Zehnder interferometer (MZI) configuration. By combining two of such half-rate (53 GBd) transmitters in an integrated 2:1-serializer, improved 106 GBd PAM-4 performance is expected without needing to compensate the inherent modulator non-linearity and without requiring faster modulators or drivers. In this paper, we present a Silicon integrated 53 GBd PAM-4 TX as a candidate for integration into 106 GBd PAM-4 2:1 serialized TX. The presented TX consists of two EAMs in an MZI configuration, wirebonded to a low-power 55 nm 4-channel SiGe BiCMOS driver, operating at 1.5 pJ/b (excluding laser). With a reference receiver (RX), transmission at or below the KP4-FEC threshold is shown beyond 1km standard single-mode fiber (SSMF) and up to 2 km non-zero dispersion-shifted fiber (NZ-DSF) at 1565 nm. Furthermore, the integrated TX was combined with an Si-integrated RX consisting of the same EAM component, wirebonded to a 55 nm SiGe BiCMOS transimpedance amplifier (TIA). Both TX and RX were wirebonded on an RF-PCB, with electrical connectivity through transmission lines and 6-inch 50 GHz multi-coax cable connectors. With this electrically connectorized all-EAM TX and RX, PAM-4 link operation is shown up to 40 GBd at 3.9 pJ/b (excluding laser), without using DSP or equalization.

Today, the datacenter ecosystems are fueling the demand for novel transmitter (ΤΧ) technologies complying with the off-board, on-board, and chip-to-chip computing needs. This has set a new class of requirements for the TX infrastructure that should now offer multiple credentials, namely: high-speed, O-band operation for avoiding dispersion compensation in long distances, wavelength-division multiplexing (WDM) capabilities for higher throughput and multicasting/broadcasting support, and tight co-packaging with low-power electronics. Silicon (Si) photonic TXs have been extensively studied toward high-speed and WDM TX engines targeting mainly C-band. Only a limited number of Si-Pho O-band TXs have been reported, however with ≤32 Gb/s/channel line-rate capabilities and with a WDM portfolio that has not been fully explored yet. In this paper, we introduce a novel silicon photonic high-speed O-band TX hardware platform that can meet the current datacom and computercom interconnect requirements. We demonstrate a ring modulator (RM) based four-channel WDM TX at 4 × 40 Gb/s non-return-to-zero (NRZ) operation that supports wavelength parallelism in unicast operation but can also pave the way toward WDM TX engines for the post-100 GbE TX era. Moreover, we present a broadband Si Mach–Zehnder modulator employed in a WDM modulation scheme of 2 × 25 Gb/s NRZ signals and demonstrate multicasting when combined with a 8 × 8 passive arrayed waveguide grating router (AWGR) wavelength router, addressing the broadcasting needs of traffic usually encountered in cache-coherent multisocket settings. Finally, we further demonstrate the tight synergy of O-band Si-RM modulators with high-speed CMOS electronics, presenting an RM-based TX assembly prototype employing a fully depleted silicon-on-insulator CMOS driver, delivering 50-Gb/s NRZ operation.

We present the design and implementation of a 90 -Gb/s non-return-to-zero (NRZ) direct detection optical receiver that consists of a low-noise transimpedance amplifier (TIA), fabricated in a 55-nm SiGe BiCMOS technology, and a Ge photodiode integrated into a Silicon Photonic integrated circuit. Low-noise broadband operation is achieved using a fully differential TIA that provides the photodiode reverse bias. 50-, 56-, and 64-Gb/s NRZ operation is demonstrated at bit-error ratios (BERs) below $10^{-12}$ at sensitivities of $-$ 12.3-, $-$ 11.2-, and $-$ 11.1-dBm optical modulation amplitude (OMA) while consuming 128, 141, and 157 mW, respectively. Furthermore, a BER below $10^{-12}$ is achieved at 80 Gb/s with a sensitivity of $-$ 6.1 dBm (OMA) at 165 mW, and operation below KP4-FEC $({2.4 \times {10}^{-4}})$ is demonstrated up to 90 Gb/s with a sensitivity of $-$ 7.1 dBm (OMA) while consuming 222 mW. All BERs were measured in real time and without DSP or equalization to compensate the receiver. The presented receiver achieves the best reported sensitivities up to 90 Gb/s, at the second-lowest power consumption, and is the first reported integrated optical RX up to 90 Gb/s that is tested in real time without any equalization or DSP to compensate the receiver. The presented optical receiver is ideally suited for upcoming short-reach applications.

We present a 70 Gb/s capable optical transmitter consisting of a 50 $\mu$ m long GeSi electro-absorption modulator (integrated in silicon photonics) and a fully differential driver designed in a 55 nm SiGe BiCMOS technology. By properly unbalancing the output stage, the driver can be dc-coupled to the modulator thus avoiding the use of on-chip or external bias-Ts. At a wavelength of 1560 nm, open eye diagrams for 70 Gb/s after transmission over 2 km standard single-mode fiber were demonstrated. The total power consumption is 61 mW, corresponding to 0.87 pJ/b at 70 Gb/s. Bit-error rate measurements at 50 Gb/s and 56 Gb/s (performed both back to back and with up to 2 km standard single-mode fiber) demonstrate large (0.4 UI at a BER of $10^{-12}$ ) horizontal eye margins. This optical transmitter is ideally suited for datacenter applications that require densely integrated transceivers with a low power consumption.

Silicon photonics is a key-enabling technology leveraging decades of effort and infrastructure of the microelectronics CMOS industry resulting in high yield, low cost and potential high volume manufacturing. Furthermore, due to the high index contrast of the platform, very compact, high-complexity photonic integrated circuits can be devised. To benefit from these advantages, high-speed modulators should also be compatible with silicon technology. In this respect, SiGe electro-absorption modulators (EAM) are considered as a promising candidate since they are CMOS-compatible and offer high-speed, compact, low-loss and low-power modulation. In this paper, we discuss SiGe EAM-based transceivers for next-generation datacenter interconnects (DCI) and radio-over-fiber (RoF) fronthaul in next-generation cellular networks.

A novel method is presented to embed finite-impulse-response filters in slow-wave Mach–Zehnder modulators. This allows to adjust the electro-optic frequency response to the designer's needs. The filter is embedded by adding optical delay lines and optical crossings between phase shifter segments. The position of the delay lines and crossing in the modulator and the delay line length determine the final response. In this work, we provide a full analysis and modeling approach of the proposed technique and apply it to a silicon photonic modulator. However, the technique is generally applicable to slow-wave modulators and thus not limited to a silicon photonics platform. The modeling is verified using measurements on the manufactured devices. A shaped modulator is used in C-band transmission experiments with 56 Gb/s NRZ data over 3 km fiber to counteract chromatic dispersion and show the advantage over a standard modulator.

Optical transmitters for four-level pulse amplitude modulation (PAM-4) have attracted a significant amount of research in recent years, in large part due to the standardization of the format for the 200 and 400 Gigabit Ethernet optical interconnects in data centers. However, combining low-power and linear operation of the electro-optical frontend with sufficiently large bandwidths has proven challenging, especially for the 100 Gb/s/λ links (i.e., employing 50 Gbaud PAM-4). The most straightforward solution has been to deal with the non-idealities of the modulator in the electrical domain: predistorting the signal levels and/or equalizing the frequency response with the help of digital signal processing (DSP). However, this typically requires fast digital-to-analog converters (DACs), either capable of delivering large swings (> 1 Vpp) or supplemented with an additional linear amplifier to drive the optical modulator. Both options substantially increase the power consumption and the complexity of the transceiver. Rather than allocating effort to linearize the electrical to optical conversion of a single modulator, we propose a topology that performs the DAC operation in the optical domain. Two compact electro-absorption modulators in an interferometer layout are driven with NRZ data to generate the four-level signal in the optical domain. Using this topology, we demonstrate the first real-time 128 Gb/s PAM-4 transmission with a silicon photonic transmitter in a chip-to-chip link. In a back-to-back setup, we obtained a bit-error ratio (BER) of 4 × 10−10 without requiring any DAC, DSP, or modulators with large traveling wave structures. Over 1 km of standard single mode fiber a BER of 8 × 10−6 is recorded, still well below the KP4 forward error-coding limit. These results correspond to the lowest BERs reported for any real-time PAM-4 link at 100 Gb/s or higher, illustrating the benefit of performing the DAC operation in the optical domain.

We present an O-band any-to-any chip-to-chip (C2C) interconnection at 40 Gb/s suitable for up to 8-socket direct connectivity in multi-socket server boards, utilizing integrated low-energy photonics for the transceiver and routing functions. The C2C interconnect exploits an Si-based ring modulator as its transmitter and a co-packaged photodiode/transimpedance amplifier enabled receiver interconnected over an 8 x 8 Si-based arrayed waveguide grating router, allowing for a single-hop flat-topology interconnection between eight nodes. A proof-of-concept demonstration of the C2C interconnect is presented at 25 and 40 Gb/s for eight possible routing scenarios, revealing clear eye diagrams at both data rates with extinction ratios of 4.8 +/- 0.3 and 4.38 +/- 0.31 dB, respectively, among the eight routed signals.

The use of four-level pulse-amplitude modulation (PAM-4) has emerged as a solution to increase the serial rate in short-range optical links, offering twice the data throughput but requiring similar bandwidth as on–off keying. However, the receiver design should take into account the increased susceptibility of PAM-4 to noise, intersymbol interference, and nonlinearity. This papers explores these challenges, and details the design of a transimpedance amplifier (TIA) for 64-Gb/s PAM-4 optical links. The TIA was implemented in 0.13-µm SiGe BiCMOS, and has a power consumption of 180 mW. It contains a digital gain controller, which allows switching between four gain modes, to tradeoff sensitivity against linearity. Bit error rate (BER) measurements show that the dynamic range is significantly extended: Optical modulation amplitudes between $-$ 7 dBm and at least $-$ 0.2 dBm yield a BER lower than $10^{-3}$ .

Avalanche photodetectors (APDs) integrated in a silicon platform have the potential to significantly improve the link budget of optical links compared with conventional p-i-n photodetectors, while only requiring CMOS-friendly biasing voltages. We demonstrate an optical receiver based on a 1310nm

Future wireless communication links will require ever decreasing cell sizes to provide massive data capacity densities. Implementing a fully operational base station in each cell is not viable and thus centralized solutions making use of radio-over-fiber (RoF) have been proposed. Transimpedance amplifiers (TIAs) are an essential component in such RoF links. In this article, resonant TIAs making use of series inductive peaking are proposed for RoF communication links. Such a band-pass approach benefits from superior noise behavior and a relaxation of the transimpedance limit compared to the traditional broadband designs typically used in RoF.

We present a low-power all-digital radio-over-fiber transmitter for beyond 28-GHz using sigma-delta modulation, a 140mW NRZ driver and parallel electro-absorption modulators. 5.25Gb/s (2.625Gb/s) 64-QAM is transported over 10-km SSMF at 1560nm with 7.6% (5.2%) EVM.

High-speed electronic integrated circuits are essential to the development of new fiber-optic communication systems. As a consequence of the increasing speeds and multi-channel operation, close integration and co-design of photonic and electronic devices have become a necessity to realize high-performance sub-systems. Such co-design on the other hand also enables the design of new electro-optic architectures to create and process multi-level optical signals. This presentation will illustrate a number of recent and ongoing developments in IDLab, an imec research group, from various H2020 projects with a focus on application-specific high-speed electronic transceiver circuits such as driver amplifiers and transimpedance amplifiers (TIAs).

We propose a novel implementation of a complex analog equalization filter for the compensation of frequency-dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate for electrical bandwidth limitations and distortion introduced by chromatic dispersion in the fiber. The complex filter is implemented by combining four distributed analog finite-impulse response (FIR) filters to obtain the necessary response. The filter delays are implemented using active delay cell structures to create a compact solution. The analog filter is implemented in a 55-nm BiCMOS technology and consumes 185-mW core power for five complex filter taps. Performance is evaluated using the S-parameter measurements, noise and linearity measurements, and real-time system experiments using 112-Gb/s 16-QAM-modulated signals.

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4 x 50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of -9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement.

We demonstrate an optical transmitter consisting of a limiting SiGe BiCMOS driver co-designed and co-packaged with a silicon photonic segmented traveling-wave Mach-Zehnder modulator (MZM). The MZM is split into two traveling-wave segments to increase the bandwidth and to allow a 2-bit DAC functionality. Two limiting driver channels are used to drive these segments, allowing both NRZ and PAM4 signal generation in the optical domain. The voltage swing as well as the peaking of the driver output are tunable, hence the PAM4 signal levels can be tuned and possible bandwidth limitations of the MZM segments can be partially alleviated. Generation of 50 Gbaud and 53 Gbaud PAM4 yields a TDECQ of 2.8 and 3.8 dB with a power efficiency of 3.9 and 3.6 pJ/bit, respectively; this is the best reported efficiency for co-packaged silicon transmitters for short-reach datacenter interconnects at these data rates. With this work, we show the potential of limiting drivers and segmented traveling-wave modulators in 400G capable short-reach optical interconnects.

A hybrid BiCMOS-Silicon Photonics receiver with a waveguide-coupled Ge/Si avalanche photodiode is demonstrated with OMA sensitivities of −14.4dBm for error-free operation at 50 Gbps and -18.6 dBm under the KP4-FEC limit at 56 Gbps NRZ-OOK.

Packaging and assembly challenges for photonic chips still need to be addressed in order to enable rapid deployment in mass-market production. Integration and assembly solutions that not only enable ease of packaging but also allow a dense co-integration of the electronic and photonic ICs are essential. In that context, we demonstrate an adaptive patterning of both optical and electrical fan-out for face-up electronic-photonic integration. For the optical fan-out, we developed an approach based on adiabatic optical coupling between single-mode polymer waveguides and silicon waveguides on a silicon photonic chip. The polymer waveguides were directly patterned on the silicon photonic chip by direct-write lithography (DWL). The electrical interconnects between a photonic chip and electronic IC are realized by employing high-speed silver interconnects using aerosol-jet printing (AJP), as a promising alternative for the traditional bond-wires. Furthermore, a direct comparison between the AJP interconnects and the conventional bondwires is established. Finally, an NRZ optical transmitter has been successfully demonstrated based on the AJP interconnection and clear open eye diagrams were obtained at 56 Gb/s.

Tightly integrated and co-optimized electronic and photonic integrated circuits are key to meet the scalability and performance requirements for next-generation optical access. We address the challenges, design considerations and methodology for such circuits at >25G rates.

Efficient packaging of integrated photonic chips (PIC) on host substrates is essential to fully deploy their potential and to co-integrate electronic chips (EIC). A high-performance electro-optical printed circuit board (EOCB), which exhibits a combined electrical and optical interface, is proposed to serve as integration platform for PICs. This enables an assembly approach which combines two assembly steps, the optical and the electrical one, into one single step. Whereby, the two processes usually operate in quite different accuracy regimes.

Four-level pulse amplitude modulation (PAM-4) is widely regarded as the modulation format of choice for the next generation of 400 gigabit Ethernet short-reach optical transceiver. However, generating and receiving PAM-4 at line rates of 112 Gb/s has proven challenging, without relying on power-hungry tools as digital signal processing and digital-to-analog converters, as it requires linearity from the E/O-components in the link and/or predistortion techniques. Moving the binary to multilevel conversion to the optical domain would greatly relax these requirements. Electroabsorption-based transceivers would be ideally suited for this type of data center interconnects as they are capable of combining low-power and high bandwidth operation with a very compact layout, removing the need for large travelling wave structures and dedicated 50 Ω terminations. In this paper, we present a novel transmitter topology for generating PAM-4 using two binary-driven electroabsorption modulators in parallel. Using this approach, we achieve superior performance with respect to a single, but identical multilevel-driven EAM. Finally, we demonstrate the first silicon-based modulator capable of transmitting single-lane 112 Gb/s PAM-4 over 2 km of standard single-mode fiber without any electrical digital-to-analog converter, DSP, or long transmission line structures and terminations.

Data centre optical links are migrating to four-level pulse amplitude modulation (PAM-4) as a method to extend the data rate while covering longer distances. Vertical-cavity surface-emitting lasers (VCSELs) enable the integration of low-power transmitters, but their non-linear and bias-dependent behaviour makes conventional feed-forward equalisation less effective. This Letter presents a 0.13 mu m SiGe BiCMOS PAM-4 driver that boosts the falling-edge to the bottom level through a selective pre-emphasis technique. Experiments at 25 GBd (50 Gb/s) reveal that adding selective pre-emphasis to a 4-tap equalised current driving a 20.6 GHz 1.5 mu m VCSEL, relaxes the critical PAM-4 link budget requirements by >1 dB at the KP4 forward error correction threshold of 2.2 x 10(-4). The potential of PAM-4 VCSEL transmitters can be significantly enhanced by including selective pre-emphasis to the equalisation topology while requiring minimal overhead.

Using two $120\ \mu m$ long, binary driven GeSi electro-absorption modulators in parallel and an in-house developed electrical transceiver chipset, we demonstrate the first real-time transmission of 128 Gb/s PAM-4 over 1 km fiber without requiring any DSP or DAC/ADC.

We present a novel integrated PAM-4 modulator based on the vector addition of 2 binary driven parallel GeSi electro-absorption modulators. Clear open eyes at 56 GBaud up to 2 km of SSMF without any DSP are demonstrated.

A cost-effective, compact, and high-performance antenna element for beamforming applications in all fifth-generation (5G) New Radio bands in the [24.25–29.5] $ \,$ GHz spectrum is proposed in this letter. The novel antenna topology adopts a square patch, an edge-plated air-filled cavity, and an hourglass-shaped aperture-coupled feed to achieve a very high efficiency over a wide frequency band in a compact footprint ( $\boldsymbol{{0.48} \lambda _0 \times \text{0.48}\lambda _0}$ ). Its compliance with standard printed circuit board (PCB) fabrication technology, without complex multilayer PCB stack, ensures low-cost fabrication. The antenna feedplane offers a platform for compact integration of active electronic circuitry. Two different modular 1 $ \boldsymbol{\times }$ 4 antenna arrays were realized to demonstrate its suitability for broadband multiantenna systems. Measurements of the fabricated antenna element and the antenna array prototypes revealed a $-$ 10 dB impedance bandwidth of 7.15 GHz (26.8%) and 8.2 GHz (30.83%), respectively. The stand-alone antenna features a stable peak gain of 7.4 $ \,\pm \,$ 0.6 $ \,$ dBi in the [24.25–29.5] $ \,$ GHz band and a measured total efficiency of at least 85%. The 1 × 4 array provides a peak gain of 10.1 $ \,\pm \,$ 0.7 $ \,$ dBi and enables grating-lobe-free beamsteering from ${-}\text{50}^\circ$ to $ \text{50}^\circ$ .