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Intracortical brain-machine interfaces have shown promise for restoring function to people with paralysis, but their translation to portable and implantable devices is hindered by their high power consumption. Recent devices have drastically reduced power consumption compared to standard experimental brain-machine interfaces, but still require wired or wireless connections to computing hardware for feature extraction and inference. Here, we introduce a Neural Recording And Decoding (NeuRAD) application specific integrated circuit (ASIC) in 180 nm CMOS that can extract neural spiking features and predict two-dimensional behaviors in real-time. To reduce amplifier and feature extraction power consumption, the NeuRAD has a hardware accelerator for extracting spiking band power (SBP) from intracortical spiking signals and includes an M0 processor with a fixed-point Matrix Acceleration Unit (MAU) for efficient and flexible decoding. We validated device functionality by recording SBP from a nonhuman primate implanted with a Utah microelectrode array and predicting the one- and two-dimensional finger movements the monkey was attempting to execute in closed-loop using a steady-state Kalman filter (SSKF). Using the NeuRAD's real-time predictions, the monkey achieved 100% success rate and 0.82 s mean target acquisition time to control one-dimensional finger movements using just 581 μW. To predict two-dimensional finger movements, the NeuRAD consumed 588 μW to enable the monkey to achieve a 96% success rate and 2.4 s mean acquisition time. By employing SBP, ASIC brain-machine interfaces can close the gap to enable fully implantable therapies for people with paralysis.

Miniaturized and wireless near-infrared (NIR) based neural recorders with optical powering and data telemetry have been introduced as a promising approach for safe long-term monitoring with the smallest physical dimension among state-of-the-art standalone recorders. However, a main challenge for the NIR based neural recording ICs is to maintain robust operation in the presence of light-induced parasitic short circuit current from junction diodes. This is especially true when the signal currents are kept small to reduce power consumption. In this work, we present a light-tolerant and low-power neural recording IC for motor prediction that can fully function in up to 300 μW/mm(2) of light exposure. It achieves best-in-class power consumption of 0.57 μW at 38° C with a 4.1 NEF pseudo-resistorless amplifier, an on-chip neural feature extractor, and individual mote level gain control. Applying the 20-channel pre-recorded neural signals of a monkey, the IC predicts finger position and velocity with correlation coefficient up to 0.870 and 0.569, respectively, with individual mote level gain control enabled. In addition, wireless measurement is demonstrated through optical power and data telemetry using a custom PV/LED GaAs chip wire bonded to the proposed IC.

ObjectiveBrain-machine interfaces (BMIs) have the potential to restore motor function but are currently limited by electrode count and long-term recording stability. These challenges may be solved through the use of free-floating “motes” which wirelessly transmit recorded neural signals, if power consumption can be kept within safe levels when scaling to thousands of motes. Here, we evaluated a pulse-interval modulation (PIM) communication scheme for infrared (IR)-based motes that aims to reduce the wireless data rate and system power consumption.ApproachTo test PIM’s ability to efficiently communicate neural information, we simulated the communication scheme in a real-time closed-loop BMI with non-human primates. Additionally, we performed circuit simulations of an IR-based 1000-mote system to calculate communication accuracy and total power consumption.Main ResultsWe found that PIM at 1kb/s per channel maintained strong correlations with true firing rate and matched online BMI performance of a traditional wired system. Closed-loop BMI tests suggest that lags as small as 30 ms can have significant performance effects. Finally, unlike other IR communication schemes, PIM is feasible in terms of power, and neural data can accurately be recovered on a receiver using 3mW for 1000 channels.SignificanceThese results suggest that PIM-based communication could significantly reduce power usage of wireless motes to enable higher channel-counts for high-performance BMIs.

Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc–dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from −20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

Piezoelectric energy harvesters (PEHs) are widely deployed in many self-sustaining systems, and proper rectifier circuits can significantly improve the energy conversion efficiency and, thus, increase the harvested energy. Various active rectifiers have been proposed in the past decade, such as synchronized switch harvesting on inductor (SSHI) and synchronous electric charge extraction (SECE). This article presents a sense-and-set (SaS) rectifier that achieves maximum-power-point-tracking (MPPT) of PEHs and maintains optimal energy extraction for different input excitation levels and output voltages. The proposed circuit is fabricated in the 0.18- $\mu \text{m}$ CMOS process with a 0.47-mm2 core area, a 230-nW active power, and a 7-nW leakage power. Measured with a commercial PEH device (Mide PPA-1022) at 85- and 60-Hz vibration frequency, the proposed circuit shows 512% and 541% power extraction improvement [figure of merit (FoM)] compared with an ideal full-bridge rectifier (FBR) for ON-resonance and OFF-resonance vibrations, respectively, while maintaining high efficiency across different input levels and PEH parameters.

Arrays of floating neural sensors with high channel count that cover an area of square centimeters and larger would be transformative for neural engineering and brain-machine interfaces. Meeting the power and wireless data communications requirements within the size constraints for each neural sensor has been elusive due to the need to incorporate sensing, computing, communications, and power functionality in a package of approximately 100 micrometers on a side. In this work, we demonstrate a near infrared optical power and data communication link for a neural recording system that satisfies size requirements to achieve dense arrays and power requirements to prevent tissue heating. The optical link is demonstrated using an integrated optoelectronic device consisting of a tandem photovoltaic cell and microscale light emitting diode. End-to-end functionality of a wireless neural link within system constraints is demonstrated using a pre-recorded neural signal between a self-powered CMOS integrated circuit and single photon avalanche photodiode.

A key challenge for near-infrared (NIR) powered neural recording ICs is to maintain robust operation in the presence of parasitic short circuit current from junction diodes when exposed to light. This is especially so when intentional currents are kept small to reduce power consumption. We present a neural recording IC that is tolerant up to 300 μW/mm(2) light exposure (above tissue limit) and consumes 0.57 μW at 38°C, making it lowest power among standalone motes while incorporating on-chip feature extraction and individual gain control.

This article presents a voice and acoustic activity detector that uses a mixer-based architecture and ultra-low-power neural network (NN)-based classifier. By sequentially scanning 4 kHz of frequency bands and down-converting to below 500 Hz, feature extraction power consumption is reduced by 4 $\times $ . The NN processor employs computational sprinting, enabling 12 $\times $ power reduction. The system also features inaudible acoustic signature detection for intentional remote silent wakeup of the system while re-using a subset of the same system components. The measurement results achieve 91.5%/90% speech/non-speech hit rates at 10-dB SNR with babble noise and 142-nW power consumption. Acoustic signature detection consumes 66 nW, successfully detecting a signature 10 dB below the noise level.

1T1MTJ spin-transfer-torque (STT)-MRAM is a promising candidate for next-generation high-density embedded non-volatile memory. This paper presents a 1-Mb 28-nm 1T1MTJ STT-MRAM with improved sensing margin and reduced power consumption. An offset-cancelled sense amplifier is proposed, using only a single capacitor, to improve sensing margin and accelerate read speed. To save write power, an in situ write-self-termination method is proposed where the sense amplifier is reconfigured without area overhead to continuously monitor the write operation and shutoff the write drivers as soon as the magnetic transition occurs in the bitcell. A prototype chip achieves 2.8- and 3.6-ns read access time at 25 °C and 120 °C, respectively. The in situ write-self-termination scheme reduces write power by 47% and 60% with 20-ns write access time at 25 °C and 120 °C, respectively.

Objective. Brain–machine interfaces (BMIs) have the potential to restore motor function but are currently limited by electrode count and long-term recording stability. These challenges may be solved through the use of free-floating ‘motes’ which wirelessly transmit recorded neural signals, if power consumption can be kept within safe levels when scaling to thousands of motes. Here, we evaluated a pulse-interval modulation (PIM) communication scheme for infrared (IR)-based motes that aims to reduce the wireless data rate and system power consumption. Approach. To test PIM’s ability to efficiently communicate neural information, we simulated the communication scheme in a real-time closed-loop BMI with non-human primates. Additionally, we performed circuit simulations of an IR-based 1000-mote system to calculate communication accuracy and total power consumption. Main results. We found that PIM at 1 kb/s per channel maintained strong correlations with true firing rate and matched online BMI performance of a traditional wired system. Closed-loop BMI tests suggest that lags as small as 30 ms can have significant performance effects. Finally, unlike other IR communication schemes, PIM is feasible in terms of power, and neural data can accurately be recovered on a receiver using 3 mW for 1000 channels. Significance. These results suggest that PIM-based communication could significantly reduce power usage of wireless motes to enable higher channel-counts for high-performance BMIs.

Dual-junction GaAs photovoltaic (PV) cells and modules at sub millimeter scale are demonstrated for efficient wireless power transfer for Internet of Things (IoT) and bio-implantable applications under low-flux illumination. The dual-junction approach meets demanding requirements for these applications by increasing the output voltage per cell with reduced area losses from isolation and interconnects. A single PV cell (150 μm × 150 μm) based on the dual-junction design demonstrates power conversion efficiency above 22% with greater than 1.2 V output voltage under low-flux 850 nm near-infrared LED illumination at 6.62 μW/mm(2), which is sufficient for batteryless operation of miniaturized CMOS IC chips. The output voltage of dual-junction PV modules with 4 series-connected cells demonstrates greater than 5 V for direct battery charging while maintaining a module power conversion efficiency of more than 23%.

High energy efficiency is a major concern for emerging machine learning accelerators designed for IoT edge computing. Recent studies propose in-memory and mixed-signal approaches to minimize energy overhead resulting from frequent memory accesses and extensive digital computation. However, their energy efficiency gain is often limited by the overhead of digital-to-analog and analog-to-digital conversions at the boundary of the compute-memory. In this paper, we propose a new in-memory accelerator that performs all computation in the analog domain for a large, multi-level neural network (NN) for the first time avoiding any digital-to-analog or analog-to-digital conversion overhead. We propose an all-analog ResNet (AAResNet) accelerator in 28-nm CMOS, achieving an energy efficiency of 1.2 µJ/inference and inference rate of 325K images/s for the CIFAR-10 and SVHN datasets in SPICE simulation.

Brain machine interfaces using neural recording systems [1]–[4] can enable motor prediction [5]–[6] for accurate arm and hand control in paralyzed or severely injured individuals. However, implantable systems have historically used wires for data communication and power, increasing risks of tissue damage, infection, and cerebrospinal fluid leakage, rendering these devices unsuitable for long-term implantation (Fig. 26.9.1, top). Recently, several wireless and miniaturized neural recording implants with various power and data transmission methods were proposed. References [7], [8] propose an electrocorticography (ECoG) recording system with near-field RF power transfer and bilateral communication, but the 0.5W Tx exceeds maximum exposure limits by 10x [8]. Ultrasonic telemetry can safely send more power than RF; however it requires mm-scale dimensions (0.8mm3 in [9]) due to bulky ultrasound transducers. On the other hand, near infrared (NIR) light can provide power transfer and data downlink via a photovoltaic cell (PV), and a data uplink via a light-emitting diode (LED). Dimensions can be scaled to 100s of microns [10], with [11] demonstrating a 0.0297mm2 neural recording system using a 50mW/mm2 light source $( of safety limit for the brain). However, this system is limited to a single channel, and since it only has a surface electrode, it can record only surface potentials (face-down, potentially blocking the light channel) or must itself be injected into brain tissue, creating significant tissue damage and danger of bleeding. In this paper, we propose $0.74\mu \mathrm{W}, 0.19\times 0.17\mathrm{mm}^{2}1\mathrm{C}$ designed for a wireless neural recording probe. It computes so-called spiking band power (SBP) [5], [12] on-chip to save 920x power while maintaining accurate finger position and velocity decoding.

Piezoelectric energy harvesters (PEHs) convert mechanical energy from vibrations into electrical energy. They have become popular in energy-autonomous IoT systems. However.’ the total energy extracted by a PEH is highly sensitive to matching between the PEH impedance and the energy extraction circuit. Prior solutions include the use of a full-bridge rectifier (FBR) and a so-called synchronous electric-charge extraction (SECE) [1], and are suitable for non-periodic vibrations. However, their extraction efficiency is low since the large internal capacitance $C_{\mathrm {p}}$ (usually 10’s of nF) of the PEH (Fig. 27.2.1) prevents the output voltage from reaching its maximum power point (MPP) under a typical sinusoidal and transient excitation $(V_{\mathrm {M}\mathrm {P}\mathrm {P}}={1/2}\cdot l_{\mathrm {p}}R_{\mathrm {p}})$. A recently proposed technique [2], [3], [4], called bias-flip, achieves a higher extraction efficiency by forcing a predetermined constant voltage at the PEH output, $V_{\mathrm {p}}$, which is then flipped every half-period of the assumed sinusoidal excitation (Fig. 27.2.1, top left). To flip $V_{\mathrm {p}},$ the energy in capacitor $C_{\mathrm {p}}$ is extracted using either a large external inductor [2], [3] or capacitor arrays [4]. It is then restored with the opposite polarity (Fig. 27.2.1, top). However, $V_{\mathrm {M}\mathrm {P}\mathrm {P}}$ of the PEH varies with sinusoidal current /.’ hence, the two fixed values of $V_{\mathrm {p}}$ in the flip-bias technique either over-or underestimate $V_{\mathrm {M}\mathrm {P}\mathrm {P}}$ for much of the oscillation cycle (pattern filled regions in Fig. 27.2.1, top right). In addition, none of the prior approaches compensate for $V_{\mathrm {M}\mathrm {P}\mathrm {P}}$-waveform amplitude changes, due to input intensity variations or decaying oscillations after an impulse, further degrading efficiency.

Wireless sensors for IoT applications have become a prominent computing class and are typically severely power constrained. IoT devices are deployed in a wide range of environments and low power consumption must be guaranteed across a wide temperature range. The combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) can achieve minimum total energy per cycle, where dynamic and leakage energy are at an optimal trade-off point [1]. However, due to the dependence of leakage on temperature and workload fluctuations over time, this optimal operating point requires runtime adjustment. Traditional approaches to track an optimal operating point involve repeated measurement of processor power inside a body-bias and supply voltage search loop. However, determining processor power consumption adds significant complexity and/or power overhead since it requires separate measurement of supply voltage and current followed by their multiplication.

Acoustic sensing is one of the most widely used sensing modalities to intelligently assess the environment. In particular, ultra-low power (ULP) always-on voice activity detection (VAD) is gaining attention as an enabling technology for IoT platforms. In many practical applications, acoustic events-of-interest occur infrequently. Therefore, the system power consumption is typically dominated by the always-on acoustic wakeup detector, while the remainder of the system is power-gated the vast majority of the time. A previous acoustic wakeup detector [1] consumed just 12nW but could not process voice signals (up to 4kHz bandwidth) or handle non-stationary events, which are essential qualities for a VAD. Prior VAD ICs [2], [3] demonstrated reliable performance but consumed significant power $(\gt 20 \mu \mathrm {W})$ and lacked an analog frontend (AFE), which further increases power. Recent analog-domain feature extraction-based VADs [4], [5] also reported $\mu \mathrm {W}-$ level power consumption, and their simple decision tree [4] or fixed neural network-based approach [5] limited broader use for various acoustic event targets. In summary, no sub $-\mu \mathrm {W}$ VAD has been reported to date, preventing the use of VADs in unobtrusive mm-scale sensor nodes.

A key challenge in the design of on-chip wake-up timers for compact wireless sensor nodes is to achieve high timing accuracy over temperature and supply voltage variation within an ultra-low power budget. We propose a gate-leakage-based frequency-locked timer with first- and second-order cancellation achieving 260 ppm/°C from −5 to 95°C. The timer consumes 224 pW at 90 Hz output frequency with 0.93%/V supply voltage dependence in the 1.1-3.3 V range.

1T1R spin-transfer-torque (STT) MRAM is a promising candidate for next-generation high-density embedded non-volatile memory [1-2]. However, 1T1R STT-MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a), sense amplifier design is challenging due to the small difference (only 2x) between the high-resistance state (R AP ) and the low-resistance state (R P ), as well as R AP degradation with increasing temperature. Moreover, R P and R AP resistance distributions shift with process variation, requiring a read reference (V ref ) that tracks process. To improve the sensing margin, several offset-cancellation methods have been reported to reduce sense amplifier mismatch [3]. However, these methods use multiple capacitors and hence incur significant area overheads. To address this issue, we propose an offset-cancelled sense amplifier that uses only a single capacitor to significantly improve the sensing margin by more than 60%. A second design challenge for STT-MRAM stems from the high current needed to flip a cell during a write operation. For non-volatile memory applications with a 10-year retention time requirement, the write current can be as high as several hundred μA. However, as shown in Fig. 30.2.1(b), the required write time varies with the state change required (0→1 or 1→0), process variation, and temperature. As a result, a fixed write time that ensures successful write for all conditions wastes a significant energy for typical or average conditions. We propose an in situ write-self-termination method to reduce write energy in most scenarios. The sense amplifier is reconfigured to continuously monitor the write operation and automatically shuts off the write drivers when the state transition is detected, without an area or timing penalty. In addition, dual dummy columns are added in each array to provide read V ref tracking of row-wise PVT variation. A 1Mb STT-MRAM was fabricated in 28nm technology, and achieves a 2.8ns read-access time at 25°C and 3.6ns at 120°C, respectively. With in-situ self-write-termination the write power is reduced by 47% with a 20ns write-access time at 25°C and by 60% at 120°C.

This article introduces a 32-kHz crystal oscillator (XO) with high energy-to-noise-ratio pulse injection at subharmonic frequency. A T/4-delay clock slicer is proposed to convert the sinusoidal crystal waveform into an output clock of 32 kHz and to introduce a delay of T/4, providing proper timing for energy injections. The output clock feeds frequency dividers and generates pulses to activate the proposed all-NMOS differential driver at 4 kHz. It enables two injections in eight periods at the peak and valley of the crystal oscillation, with the crystal running freely between injections. This configuration achieves a 2-ppb Allan deviation floor. The less frequent injections reduce the injection overhead, enabling the lowest reported power consumption of published nW XOs (0.51 nW). At 0.45 V, the proposed XO operates across a temperature range of −25∘C to 125 °C, the widest reported range for nW XOs. This design is fabricated in the 40-nm CMOS and occupies 0.02 mm 2 .

This paper proposes a 2.2 noise efficiency factor (NEF) instrumentation amplifier for neural recording applications. A parametric amplifier based on the MOS C-V characteristic is designed as a pre-amplifier stage, lowering the input referred noise of the following stages by 3.4×. Sampling noise is minimized by oversampling the input signal and switching power is reduced by adopting an 8-phase soft-charging technique.

This letter proposes an instrumentation amplifier for neural recording applications whose measured noise efficiency factor (NEF) is 2.2. A discrete-time parametric amplifier is adopted as a preamplification stage to lower the input-referred noise, thus improving the NEF. The additional induced sampling noise is minimized by oversampling, and the power overhead for switching is minimized by adopting an 8-phase soft-charging technique.