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The objective of this study is to evaluate the effect of slip ratio on the wear and rolling contact fatigue (RCF) of wheel/rail materials using a rolling–sliding wear testing apparatus. The results indicate that two wear types are presented in terms of wear rate: type I (mild wear) and type II (severe wear). In type I wear, cracks propagate parallel to the surface. While in type II, the peeling is aggravated and spalling can be observed. With the slip ratio increasing, the wear mechanism of rollers transforms from slight oxidation wear and peeling to severe fatigue wear and spalling. Due to the mild wear and light plastic deformation in type I, the angle and depth of cracks show no obvious differences between the wheel and rail rollers. The crack depth and angle increase in type II wear owing to severe plastic deformation, while the depth is smaller on the wheel rollers. The size of flake wear debris presents an increasing trend and the main composition is Fe 2 O 3 and metallic iron, and the content of iron diminishes with increasing oxidation.

The aim of this study is to explore the wheel/rail adhesion restoration performance of alumina particles and the comparison between the continuous and single application test strategies in twin disc simulation. The results indicate that the single application test strategy performs better on evaluating the adhesion restoring ability of solid particles. In the single application tests, the restored adhesion coefficient increases with the applied alumina quantity and final gets stable when the quantity exceeds 2 g (0.607 g/m). However, the increase of alumina quality could always extend the duration of restored adhesion. The alumina particles at the size in the range of 0.075–0.15mm showed the best adhesion restoration and the longest duration was achieved at the size of 0.15 mm. In addition, it is observed that the serious damage is mainly caused in the particles crushing process, and will be gradually ground off in the following long running to have no threat on the serving life of the wheel and the rail. and the rail. Cílem studie bylo objasnit schopnost částic oxidu hlinitého obnovovat a udržovat přijatelnou adhezi ve vodou kontaminovaném kontaktu kola a kolejnice. V této studii byly porovnány dvě možnosti aplikace těchto částic: jednorázová a kontinuální aplikace. Výsledky ukazují, že rychlejší obnovy adheze je dosaženo při jednorázové aplikaci částic. V tomto případě bylo zjištěno, že se zvyšováním aplikovaného množství částic dochází k rychlejší obnově adheze a současně dochází také k prodlužování časového intervalu, kdy adheze nabývá požadovaných hodnot. Tento závěr je platný pro aplikovaná množství do 2 g (0,607 g/m). Nejlepší obnovy adheze bylo docíleno v případě, že se velikost části pohybovala v intervalu od 0,07 do 0,15 mm. Částice o velikosti 0,15 mm současně nejdéle udržovaly adhezi na přijatelné úrovni. Analýza povrchu ukázala, že největší poškození povrchů nastává ihned po aplikaci částic, kdy dochází k drcení těchto částic v kontaktu.

A three-dimensional thermal model that the grinding wheels are simplified as a moving heat source in the rail grinding process was established and used to explore the effect of grinding parameters on the temperature field of ground rail. The results indicate that the highest temperature of ground rail increases with an increase in the grinding power. The increase of grinding surface width and moving velocity causes a fall of ground rail temperature. It should be noted that the temperature of ground rail would continue to rise when the first car with 12 grinding wheels passes through the rail surface. However, the temperature does not increase when the second car passes through. Compared with distributing on the same grinding surfaces, two grinding wheels distributing on two adjacent grinding surfaces would lower grinding rail temperature. The results are beneficial to improve the reasonable arrangement of grinding wheels in the rail grinding process.

The objective of this study is to construct wear mapping and transitions of wheel/rail materials under different contact pressure and sliding velocity conditions by means of comprehensive consideration of both wear rates and surface damage morphology of wheel/rail rollers. The results indicate that, both the wear rates of wheel rollers and the wear rates of rail rollers increase with contact pressure increasing. With sliding velocity increasing, the wheel wear rates show an increase trend and the rail wear rates decrease. Wear regime maps of wheel/rail materials are divided into two regions: mild wear regime and severe wear regime, and both the wear rates of wheel roller and the wear rates of rail roller are about 2.0×10 −6 g/m on the transition boundaries. The wear mechanisms of the wheel and rail materials are significantly different and transform in different wear regimes. Based on the damage characteristics in different wear regimes, the wear mechanism maps of wheel and rail materials are constructed. Fatigue cracks of wheel material develop along with soft ferrite lines in the plastic deformation area. Furthermore, cracks on the rail rollers develop into the material a depth, then become parallel with the surface and turn towards it.

In this paper, we discuss the advantages and opportunities presented by high-speed ( $>$ 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon–germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs) . We compare circuit designs between generations of IBM's SiGe process, including a recent 9HP process featuring devices with a cutoff frequency $(f_{T} ) $ of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC and a 48 $\times$ 48 cell field-programmable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device ( $f_{T}=$ 825 GHz) having 100 $\times$ less power consumption than conventional vertical HBTs.

The objective of this study is to investigate the braking tribological characteristics of two kinds of metro brake shoe materials using a sub-scale frictional braking machine. The results indicate that the friction coefficient of braking interface has a close relationship with the velocity and pressure. The increase of velocity and pressure raises the temperature-rise of braking interface. The increasing velocity and pressure aggravate the wear of brake shoe rings. However, the wear loss of wheel rings decreases with increasing pressure. The braking surface of brake shoe rings exhibits adhesive wear and spalling, while obvious plowing and abrasive wear are dominant on the braking surface of wheel rings. According to the experimental results, it is concluded that brake shoe B material can be used to prevent and alleviate the occurrence and evolution of groove wear on wheel tread. This might be attributed to the higher percentage of FeC3 versus FeS2 in its composition compared with brake material A. Field testing, completed to 100,000 km thus far, has to be completed on these materials and further work should be performed for evaluating the effect of different brake shoe materials on the groove wear of wheel tread in the field.

The objective of this study is to investigate the effects of rotational speed on rolling wear and damage behaviors of wheel/rail materials using a rolling–sliding wear testing apparatus. The results indicate that, with the rotational speed increasing, the surface hardness of rail roller remains unchanged while the increase of surface hardness of wheel roller declines resulting in a decrease of wheel/rail hardness ratio. The wear loss of wheel roller increases while the wear loss of rail roller declines with increasing rotational speed. The worn surface of rail roller exhibits peeling and spalling damage. Fatigue cracks and adhesive wear are dominating for the worn surface of wheel roller. Furthermore, with the speed increasing the fatigue damage lightens and adhesive wear worsens for the wheel roller. Fatigue cracks of wheel rollers grow along with soft ferrite lines in plastic deformation area. Cracks of rail rollers tend to turn towards the worn surface. There are visible branch cracks and multilayer cracks on the surface of wheel/rail rollers. Branch cracks of wheel rollers are longer than that of rail roller, and the interlayer material of multilayer cracks is easy to break. Wear debris of wheel/rail rollers is composed of Fe2O3 and martensite. The size of debris with flakes structure decreases and the martensite content increases with the rotational speed increasing.

The aim of this study is to investigate the influence of laser cladding Fe-based alloy on microstructure and wear characteristic of wheel/rail materials using a rolling–sliding wear testing apparatus. Especially, the effect of lanthanum oxide on the properties of laser cladding coating was explored in detail. The results show that the laser cladding Fe-based alloy coating consists of dendrites and eutectic and is composed of (Fe, Ni) solid solution and Cr 7 C 3 carbide. The hardness and wear-resistance of wheel/rail materials are enhanced using laser cladding. The wear and surface damage of wheel/rail rollers dramatically alleviate owing to the refinement of the microstructure when adding lanthanum oxide into laser cladding coating. The wear mechanism of wheel/rail rollers turns from severe spalling and delamination wear (untreated specimens) to slight peeling (with 1.2% La 2 O 3 ). Furthermore, the plastic deformation of wheel/rail rollers undergoing laser cladding is significantly thinner than that of untreated rollers. In summary, laser cladding Fe-based alloy coating can be used to prolong the wear life of wheel and rail materials.

This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16 GFC and consumes 385 m W/link.

We present a rigorous electrical and optical analysis of a strained and graded base SiGe Heterojunction Bipolar Transistor (HBT) electrooptic (EO) modulator. In this paper, we propose a 2-D model for a graded base SiGe HBT structure that is capable of operating at a data bit rate of 80 Gbit/s or higher. In this structure, apart from a polysilicon/monosilicon emitter (Width = 0.12 μm) and a strained SiGe graded base (Depth = 40 nm) , a selectively implanted collector (SIC) (Depth = 0.6 μm) is introduced. Furthermore, the terminal characteristics of this new device modeled using MEDICI are closely compared with the SiGe HBT in the IBM production line, suggesting the possibility of fast deployment of the EO modulator using established commercial processing. At a subcollector depth of 0.4 μm and at a base-emitter swing of 0 to 1.1 V, this model predicts a rise time of 5.1 ps and a fall time of 3.6 ps. Optical simulations predict a π phase shift length (Lπ) of 240.8 μm with an extinction ratio of 7.5 dB at a wavelength of 1.55 μm. Additionally, the tradeoff between the switching speed, Lπ and propagation loss with a thinner subcollector is analyzed and reported.

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGA's capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10 Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands.

We analyzed an electro-optic modulator consisting of a heterojunction bipolar transistor (HBT) with graded SiGe composition in the base. Simulation shows single mode operation is attainable with an interaction length Lp of 40.8μm.

FPGAs have been a popular topic among electrical engineers for over a decade. Modern FPGAs are denser, faster and use less power compared to PLD and CPLD. This paper presents a high speed FPGA that operates in the gigahertz range. An improved reconfigurable circuit is described. State-of-the-art IBM SiGe BiCMOS technology is used to realize this high speed FPGA. A measurement on a fabricated chip proves that this FPGA is capable of operating at 11 GHz, a SONET OC-192 standard, for optical applications.

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has always been on a rise. This was never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 10-220 MHz using CMOS. The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5 GHz were reported by B. S. Goda and Channakeshav et al. using SiGe 5HP technology. Using IBM's new 7HP technology, SiGe HBT devices with cutoff frequencies (f/sub T/) over 100 GHz can be fabricated. Apart from the improvement in device speed, architectural changes have been made to improve the speed and reduce the power. This paper is mainly going to elaborate on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGA. The entire Configurable Logic Block (CLB) has been implemented using 3 Current Mode Logic (CML) trees. The power consumption of the redesigned CLB is "5.04 mW - sequential, 3.36 mW - combinational" and the maximum operating frequency of the new logic cell is 11.7 GHz. Apart from these, 2 memory planes have been added to change the personality of the FPGA dynamically. The original Widlar current mirror has been replaced by a CMOS current mirror which avoids the loading effect.

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

The low operating speed of current CMOS Field Programmable Gate Arrays (FPGAs), i.e., 10-220 MHz, has prevented their use in high-speed digital applications. With the advent of IBM Silicon Germanium (SiGe) 7HP technology, designers have been able to design FPGAs operating in the gigahertz range. This paper is going to elaborate on the implementation of a 4-bit ripple-carry full adder (FA) on the new SiGe FPGA with new architectures and a novel power management strategy. The 1-bit FA can be realized in three Configurable Logic Blocks (CLBs). Apart from these, the FA can operate in multiple modes: FAST, NON-CRITICAL, SLOW and OFF. The propagation delays of the 1-bit FA and 4-bit ripple-carry FA are 240 ps and 675 ps respectively in the FAST mode. All the simulation and layouts were done using Cadence 4.4.6 and IBM SiGe 7HP design kit version 1.1.1.0.

This paper presents an improved Xilinx XC6200 FPGA using IBM SiGe BiCMOS technology. The basic cell performance is greatly enhanced by eliminating redundant signal multiplexing procedures. The simulated combinational logic result has a 30% shorter gate delay than the previous design. By adjusting and properly shutting down the CML current, this design can be used in lower-power consumption circuits. The total saved power is 50% of the first SiGe FPGA developed in the same group. Lastly, the FPGA with a 3-D stacked memory concept is described to further reduce the influence of parasitics generated by the memory banks. The circuit area is also reduced to make dense integrated circuits possible.

Field Programmable Gate Arrays (FPGAs) have always been used for applications like signal processing, rapid prototyping etc. With the advent of SiGe HBT devices, FPGAs have found new applications in high-speed digital-system design. Since SiGe HBTs can be used along with CMOS, it has made SiGe devices very popular. This paper elaborates new ideas in designing high-speed SiGe BiCMOS FPGAs. The architecture is based on Xilinx 6200. The paper explains new methods to cut down the number of trees in the circuit. Selective tree shutdown has been used to reduce power consumption. A new decoding logic has been developed where the address and data lines are shared. These ideas have improved the performance of SiGe FPGAs. The operating frequencies of the new Configuration Logic Block (CLB) is in the range of 1-20 GHz.

Implementation of a silicon germanium (SiGe) field programmable gate array (FPGA) has been described. The reconfigurable basic cell (BC) that evolved from the Xilinx XC6200 has been redesigned to achieve high speed with lower power consumption. The propagation delay of the BC in comparison to the BC implemented in the earlier generation SiGe process has been reduced to 18% of its original value (from 240 to 42 ps) and the power consumption has been comparably reduced. The range of power reduction is from 13% of its original value when the BC is fully turned on down to 2% when the power saving scheme is applied. A 20times20 SiGe FPGA with physical dimensions of 4.5times4.8 mm has been fabricated using the IBM 120 GHz (7HP) process. To deliver a 10 GHz clock, an H tree has been designed and implemented with reduced skew. To demonstrate its performance, a 4:1 multiplexer (MUX) has been mapped for comparison with various CMOS FPGAs. The SiGe FPGA can achieve an 8 Gbps transmission rate, which is a 40 times improvement over the same implementation on a Xilinx Virtex CMOS FPGA. Other comparisons between the SiGe FPGA and commercial FPGAs have also been included. From simulations and measurements, the SiGe FPGAs have been shown to have high performance that can successfully tackle gigahertz applications