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Recently, incinerators have been shifted to underground complexes because of concerns regarding environmental pollution and declining land prices. In Korea, an underground waste incinerator has been built for the first time, with additional construction being expected in the near future. Therefore, a perception survey was conducted to acquire responses from South Korean experts regarding the impact of underground complex incinerators. The Q-methodology was used in the survey to examine various viewpoints. Academicians showed concerns regarding environmental effects of ground incinerators, and environmental and economic effects of underground complex incinerators, conversely, industrialists were concerned about civil complaints and administrative processing, indicating that the academicians were more concerned about scientific issues, whereas the industrialists were more concerned about democratic issues. Furthermore, both groups expressed concerns regarding land value and civil complaints of ground incinerators, safety issues and resultant social distrust of underground incinerators. The findings suggest that, to address the safety issues involving underground incinerator construction, governance by local experts is required for a holistic evaluation of environmental issues and economic feasibility of underground incinerators. To establish a link between science and democracy, measures for transparently sharing information are necessary.

We apply our hot-carrier degradation (HCD) model, which uses the information about the carrier energy distribution, to represent HCD data measured in n- and p-channel LDMOS transistors. In the first version of our model we use the spherical harmonics expansion approach to solve the Boltzmann transport equation (BTE), while in the second version we employ the drift–diffusion scheme. In the latter case the carrier energy distribution function is approximated by an analytic expression with parameters found using the drift–diffusion scheme. The model, which has already been verified with nLDMOS transistors, is used to represent the carrier distribution functions, interface state density profiles, and changes of the drain currents vs. stress time in pLDMOS transistor. Particular attention is paid to study the role of the cold fraction of the carrier ensemble. We check the validity of the model by neglecting the effect of cold carriers in HCD modeling in the case of nLDMOS devices stressed at high voltages. In our model, cold carriers are represented by the corresponding term in the analytic formula for the carrier distribution function as well as by the multiple-carrier process of the Si–H bond dissociation. We show that even in high-voltage devices stressed at high drain voltages the thermalized carriers still have a substantial contribution to HCD.

We propose a dual output dc/dc converter for high efficiency and small form factor in electric bike applications. To implement a converter with single input of 48 V and dual output of 5 V and 12 V, we propose the system architecture combined with a 48-to-12 V converter and a 12-to-5 V converter on single PCB. The input of the 12-to-5 V is connected to the output of the 48-to-12 V converter to obtain stable 5 V without regard to the battery voltage. For high efficiency, both converters use synchronous topologies. For small form factor, the switching frequencies of the converters are fixed to 300 kHz and 1 MHz, respectively. To minimize undesirable PCB noise, several resistors are added and signal paths are designed shortly. The proposed dual output converter was implemented to 45 mm × 42 mm size. When the input voltage of 48 V is supplied, the measure efficiency is 87.5 % under a full-load condition of 3.1 A at 5 V output and 2 A at 12 V output.

We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method, while the second uses the simpler drift-diffusion (DD) scheme. We compare these two versions of our model and show that both approaches can capture HCD. We, therefore, conclude that in the case of nLDMOS devices, the DD-based variant of the model provides good accuracy and at the same time is computationally less expensive. This makes the DD-based version attractive for predictive HCD simulations of LDMOS transistors.

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.

The interface state density profile for an unstressed transistor has been carefully extracted. The experimental evidence of profile non-uniformity is presented. A scheme to separate the bulk oxide trap contribution from the total charge pumping current is suggested as an improvement to the conventional extraction procedure. The obtained information is of high importance in the context of hot-carrier degradation modeling in order to allow for a more detailed verification of the model.

We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.

This paper presents the results of hot carrier stress experiments of a high voltage 0.35 μm n-channel lateral DMOS transistor. The stress induced degradation was investigated at different ambient temperatures over a wide range of both gate- and drain-stress voltages. In order to explain the observed device degradation under these stress conditions, the combined influence of hole- and electron induced degradation have to be taken into account. A physical explanation of the observed effects is provided and a phenomenological degradation model is suggested.

We model hot-carrier degradation (HCD) in n- and p-channel LDMOS transistors using an analytic approximation of the carrier energy distribution function (DF). Carrier transport, which is an essential ingredient of our HCD model, is described using the drift-diffusion (DD) method. The analytical DF is used to evaluate the bond-breakage rates. As a reference, we also obtain the DF from the solution of the Boltzmann transport equation using the spherical harmonics expansion (SHE) method. The distribution functions and interface state density profiles computed using the SHE and DD-based approaches are compared. The comparison of the device degradation characteristics simulated by these two approaches with the experimental data shows that the DD-based variant, which is considerably less computationally expensive, provides good accuracy. We, therefore, conclude that the DD-based version is efficient for predictive HCD simulations in LDMOS devices.

We present a physical model for hot-carrier degradation (HCD) which is based on the information provided by the carrier energy distribution function. In the first version of our model the distribution function is obtained as the exact solution of the Boltzmann transport equation, while in the second one we employ the simplified drift-diffusion scheme. Both versions of the model are validated against experimental HCD data in nLDMOS transistors, namely against the change of such device characteristics as the linear and saturation drain currents. We also compare the intermediate results of these two versions, i.e. the distribution function, defect generation rates, and interface state density profiles. Finally, we make a conclusion on the vitality of the drift-diffusion based version of the model.

In this work the influence of nanoscale particles caused by processing excursions during back end of line (BEOL) processing on top of the photodiode active region was examined. To investigate the influence of the particles on the photodiode performance, wafer level optical responsivity measurements were done. In addition to the measurements the effect of the particles was simulated with a simplified model based on a modified transfer matrix method (MTMM)1 . The simulation and measurements are in very good agreement with each other and lead to the conclusion that even though some decrease of sensitivity was observed, the overall system variability was reduced by the presence of particles. Furthermore, the influence of the dielectric stack layer thickness variability on the photon flux density is reduced.

We present two schemes for carrier transport treatment to be used with our hot-carrier degradation (HCD) model. The first version relies on an exact solution of the Boltzmann transport equation (BTE) by means of the spherical harmonics expansion (SHE) method, whereas the second one uses a simplified drift-diffusion (DD) scheme to avoid the computationally expensive SHE approach. We use both versions of the model to simulate the change of the characteristics of an nLDMOS transistor subjected to hot-carrier stress and compare these theoretical degradation traces with the experimental ones. The similarity in the results of the SHE- and DD-based models together with the flexibility of the latter approach makes it attractive for fast and predictive HCD simulations for LDMOS devices.

The quality of the numeric approximation of the partial differential equations governing carrier transport in semiconductor devices depends particularly on the grid. The method of choice is to use structurally aligned grids since the regions and directions therein that determine device behavior are usually straightforward to find as they depend on the distribution of doping. Here, the authors present an algorithm for generating structurally aligned grids including anisotropy with resolutions varying over several orders of magnitude. The algorithm is based on a level set approach and permits to define the refined resolutions in a flexible manner as a function of doping. Furthermore, criteria on grid quality can be enforced. In order to show the practicability of this method, the authors study the examples of a trench gate metal-oxide-semiconductor field-effect transistor (TMOSFET) and a radio frequency silicon-on-insulator lateral double diffused metal-oxide-semiconductor (RF SOI LDMOS) power device using the device simulator MINIMOS NT, where simulations are performed on a grid generated by the new algorithm. In order to resolve the interesting regions of the TMOSFET and the RF SOI LDMOS power device accurately, several regions of refinement were defined where the grid was grown with varying resolutions.

We describe new SOI lateral power devices which have a trench oxide to improve the device performance. Highvoltage super-junction (SJ) SOI-LDMOSFETs have a trench oxide in the drift region. It allows to reduce the drift length without degrading the breakdown voltage. With the proposed device structure a reduction of the on-resistance of the n-drift layer can be achieved. The breakdown voltage and the specific on-resistance of the suggested devices as a function of the trench oxide depth, the p-column width, and the doping are studied. Shorted-anode lateral insulatedgate bipolar transistors (SA-LIGBTs) on SOI have a trench oxide at the drain/anode region. It suppresses effectively the snap-back voltage inherent in conventional SA-LIGBTs without increasing the anode length of the device. Using the two-dimensional numerical simulator Minimos-NT, we confirm that the drift length of the proposed SJ SOILDMOSFETs is reduced to 65% compared to conventional devices, and a weak negative differential resistance region is observed with the proposed SOI SA-LIGBT. � 2004 Elsevier Ltd. All rights reserved.

We present a lateral trench gate SOI-LDMOSFET that uses narrow trenches as channels. The lateral trench gate, which allows the channel current to flow laterally on the trench side walls, decreases its on-resistance because it increases the current spreading area of the device. The specific on-resistance ðRspÞ strongly depends on the trench depth, which affects the channel area on the side wall of the trench and the space between the trenches affects the channel density of the device. The Rsp of the suggested devices as a function of the lateral trench depth and the space between the trenches are studied. Three-dimensional numerical simulations with MINIMOS-NT have been performed to investigate the influence of device parameters on the Rsp and the breakdown voltage. The improvement in the current handling capability of the suggested device is about 8.3% compared to the conventional SOI-LDMOSFET. q 2003 Elsevier Ltd. All rights reserved.

The high-voltage and self-heating behavior of partial-SOI (silicon-on-insulator) LDMOSFETs were studied numerically. Different locations of the silicon window were considered to investigate the electrical and thermal effects. It is found that the potential distribution of the partial-SOI LDMOSFET with the silicon window under the drain is similar to that of standard junction isolation devices. With the silicon window under the source the potential distribution is similar to that of the conventional SOI LDMOSFET. Using the two-dimensional numerical simulator MINIMOS-NT, we confirm that the breakdown voltage of partial-SOI LDMOSFETs with a silicon window under the source is higher than that of partial-SOI LDMOSFET with a silicon window under the drain.

Our physics-based HCD model has been validated using scaled CMOS transistors in our previous work. In this work we apply this model for the first time to a high-voltage nLDMOS device. For the calculation of the degrading behaviour the Boltzmann transport equation solver ViennaSHE is used which also requires high quality adaptive meshing. We discuss the influence of the different model components in the different device regions. Finally we compare the model to experimental degradation results and show that each one gives a significant contribution to the result and that all of them are needed in order to satisfactorily fit the experimental data.

Using our physics-based model for hot-carrier degradation (HCD) we analyze the role of such important processes as the Si-H bond-breakage induced by a solitary hot carrier, bond dissociation triggered by the miltivibrational excitation of the bond, and electron-electron scattering. To check the roles of these mechanisms we use planar CMOS devices with gate lengths varying between 65 and 300 nm as well as a high-voltage nLDMOS transistor. We show that the current HCD paradigm needs to be revised because the aforementioned processes can be crucial even under stress conditions at which they are supposed to be weak.

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.

The 0.35μm HV-CMOS process technology utilizes several junctions with different doping levels and depths. This process supports complete modular 3V and 5V standard CMOS functionality and offers a wide set of HV transistor types capable for operating voltages from 20V to 120V made available with only 2 more mask adders [1]. Compared to other reported integration of photo detection functionalities in normal CMOS processes [2] or special modified process technologies [3] a much wider variety of junction combinations is already intrinsically available in the investigated technology. Such junctions include beside the standard n+ and p+ source/drain dopings also several combinations of shallow and deep tubs for both p-wells and n-wells. The availability of junction from submicron to 7μm depths enables the selection of appropriate spectral sensitivity ranging from ultraviolet to infrared wavelengths. On the other side by appropriate layouts the contributions of photocurrents of shallower or deeper photo carrier generation can be kept to a minimum. We also show that by analytically modelling the space charge regions of the selected junctions the drift and diffusion carrier contributions can be calculated with a very good match indicating also the suppression of diffusion current contribution. We present examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 380-450nm, 450-600nm or 700-900nm. By appropriate junction choice the ratios of the generated photo currents in their respective peak zones can exhibit more than a factor of 10 compared to the other photo diode combinations. This enables already without further filter implementation a very good spectral resolution for colour sensing applications. Finally the possible junction combinations are also assessed by the achievable dark current for optimized signal to noise characteristic.

We analyze the impact of oxide thickness variations on hot-carrier degradation. For this purpose, we develop an analytical approximation of our hot-carrier degradation (HCD) model. As this approximation is derived from a physics-based model of HCD, it considers all the essential features of this detrimental phenomenon. Among them are the interplay between single- and multiple-carrier mechanisms of interface state creation as well as the strong localization of the damage near the drain end of the gate. Both single- and multiple-carrier processes are controlled by the carrier acceleration integral which is calculated using information on the carrier energy distribution function. In the TCAD version of the model these functions are obtained from a solution of the Boltzmann transport equation by means of the Monte-Carlo method, which is computationally very expensive. To avoid that, an analytical expression which represents the carrier acceleration integral has been proposed. This expression provides an analytical dependences of the interface state density and the linear drain current change vs. time. Moreover, it allows us to incorporate the impact of variations in device architectural parameters on the acceleration integral and, hence, on HCD. As an example, we apply this strategy to describe the effect of variations in the oxide thickness on the linear drain current degradation (ΔI dlin ) during a hot-carrier stress. We demonstrate that the oxide thickness change substantially impacts ΔI dlin in a wide range of stress times.

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•10 12 /cm 3 . In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•10 13 /cm 3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm 2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

This work reports the hot-carrier (HC) behavior and specific on-resistance (R on,sp ) optimization of 20∼60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×105 sec stress), and it shows an excellent R on,sp -BV trade-off (pLDMOS with 20V GOX: BV = −85 V and R on,sp = 1.64 mΩ-cm2).

We have analyzed the worst-case conditions of hot-carrier induced degradation for high-voltage n- and p-MOSFETs with our model. This model is based on the evaluation of the carrier distribution function along the Si/SiO 2 interface, i.e. on thorough consideration of carrier transport. The distribution function obtained by means of a full-band Monte-Carlo device simulator is used to calculate the acceleration integral, which controls how effectively the carriers are breaking Si - H bonds. Therefore, we analyze the worst-case conditions using this integral as a criterion. We compare the simulated picture with the experimental one and conclude that the model fits the experimental data precisely well for both transistor types.

We propose a physics-based model for hot-carrier degradation (HCD), which is able to represent HCD observed in n-channel high-voltage MOSFETs with different channel length with a single set of physical parameters. Our approach considers not only damage produced by channel electrons but also by secondary generated channel holes. Although the contribution of the holes to the total defect creation is smaller compared to that of electrons, their impact on the linear drain current is comparable with the electronic one. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.

For competitive high-voltage (HV) integrated circuit (IC) products an excellent trade-off between specific on-resistance Ron,sp and breakdown voltage BV of a HV lateral DMOS (LDMOS) transistor, while keeping low fabrication cost, is mandatory. This paper presents a review of the HVIC technology trend with special emphasis on cost effective 0.35 μm and 0.18 μm HV-CMOS technologies. Through optimized process setup and device engineering a very competitive Ron,sp-BV trade-off of a HV LDMOS transistor without degrading the low-voltage (LV) CMOS performance has been achieved. A 0.35μm HV-CMOS technology with LDMOS transistor operating voltages from 20V to 120V is reported. Only two mask level adders on top of standard CMOS are required to provide the full set of 3.3V, 5V and 20V-120V HV devices. This is the result of taking advantage of predictive TCAD which enables early optimization of device layouts and dopant concentrations. In addition, HV and LV process integration issues of a 0.18 μm HV-CMOS technology, which play a key role to efficiently implement a HV module into a deep submicron CMOS process, are described. Key issues of p-channel LDMOS transistors are reviewed. The hot-carrier (HC) behaviour of a 50 V p-channel LDMOS transistor is presented too.

Using a physics-based model for hot-carrier degradation we analyze the worst-case conditions for long-channel transistors of two types: a relatively low voltage n-MOSFET and a high-voltage p-LDMOS. The key issue in the hot-carrier degradation model is the information about the carrier energetical distribution function which allows us to asses the carrier acceleration integral determining the interface state build-up and which controls the interplay between the single- and multiple-carrier mechanisms of Si-H bond rupture. To analyze the worst-case conditions we generate intensity maps, i.e. dependences of some crucial quantities on source-drain V ds and gate V gs stress voltage. These quantities are the boundary of the high-energy tail of the energy distribution function, the interface state generation rate and the total dose of degradation. The difference between positions of severest degradation spots evaluated according different criteria is also plotted as a function of stress voltages. Using these maps we demonstrate that the worst-case conditions are realized at 0.4V ds gs ds for the n-MOSFET and at the maximal gate current for p-LDMOS. These findings correspond to experimental results published in the literature.

We propose and verify a model for hot carrier degradation based on the exhaustive evaluation of the energy distribution function for charge carriers in the channel by means of a full-band Monte-Carlo device simulator. This approach allows us to capture the interplay between “hot” and “colder” electrons and their contribution to the damage build-up. In fact, particles characterized by higher energy are able to produce interface traps by a single-carrier process while colder ones trigger multivibrational mode excitation of a Si-H bond. For the model validation we use long-channel MOSFETs and represent the degradation of the linear drain current. The single-carrier component dominates degradation (this is the usual tendency for long devices), however, the multiple-carrier process is still considerable being less and less pronounced as the source-drain stress voltage increases

The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.

This paper presents an isolated high voltage (HV) p- channel lateral double diffused MOS (LDMOS) transistor integrated in a commercial 0.35mum CMOS process without any additional mask or implant steps and thus without increasing process complexity. It is shown that by the introduction of carefully controlled PWELL stripes in the drift region, an increase in breakdown voltages (VB) of LDMOS transistors from 10 to up to 25 V can be achieved. For the huge field of power management and automotive applications this approach of integration allows optimization for multiple voltage domains and guarantees high quality levels at an economical price level.

This paper presents the self-heating effects on the hot carrier induced degradation in high-voltage 0.35 μm lateral PMOS transistors. Hot carrier and NBTI (negative bias temperature instability) stress experiments were performed on the 50 V lateral PMOS transistors. During hot carrier stress a large shift of the threshold voltage is observed for devices with high drain current during hot carrier stress. On the contrary, thanks to the suppression of the impact ionization at the bird's beak region by proper choice of device structure and drift dose, the degradation of linear current is negligible throughout the devices. This behavior is similar to NBTI degradation. Device simulations show a high temperature increase by the self-heating at the channel region under the hot carrier stress. It is believed that the self-heating effects play a major role in the threshold voltage shift for our 50 V lateral PMOS transistors.

This paper describes the hot-carrier (HC) behaviour of a high-voltage 0.35 µm n-channel lateral DMOS transistor (LDMOSFET). Self-heating effects during HC stress have to be taken into account for the HC stress analysis. Peak Idlin and Idsat degradations were observed at the stress bias VG = 0.8 V and VG = 2.5 ∼ 3.0 V, respectively. Together with TCAD simulations and measurements, one can clearly explain the HC effects occurring near the bird’s beak region and show their impact on the Idlin and Idsat degradations.

The error of the numeric approximation of the semiconductor device equations particularly depends on the grid used for the discretization. Since the most interesting regions of the device are generally straightforward to identify, the method of choice is to use structurally aligned grids. Here, we present an algorithm for generating structurally aligned grids, including anisotropy, and for producing grids whose resolution varies over several orders of magnitude. Furthermore, the areas with increased resolution and the corresponding resolutions can be defined in a flexible manner and criteria on grid quality can be enforced. The grid generation algorithm was applied to sample structures which highlight the features of this method. Furthermore we generated grids for the simulation of a high voltage trench gate MOSFET. In order to resolve the junction regions accurately, four regions were defined where the grid was grown in several directions with varying resolutions. Finally device simulations performed by MINIMOS NT show current voltage characteristics and the threshold voltage.

We present a new accumulation-mode structure for silicon carbide laterally diffused MOSFETs. Key parameters that alter the device performance have been optimized using the device simulator MINIMOS-NT. The relationship between blocking and driving capability of the structure has been analyzed. Excellent I-V characteristics with significant improvement in the reduction of the gate bias voltage has been achieved. A blocking voltage of 1460 V with a small leakage current, a considerably lower specific on resistance of 93 m/spl Omega//spl middot/cm/sup 2/ and a fairly large advantage in electrical performance and device reliability were achieved.

The authors discuss the dependence of the breakdown voltage and temperature distribution on the location of the silicon window. They numerically confirm that the breakdown voltage of P-SOI LDMOSFET with a silicon window under the source is higher than that of P-SOI LDMOSFET with a silicon window under the drain.

IN lithographic processing to define patterns on the high reflective substrate, ARLs (anti-reflective layers) not only enable better line width control but also realize designs that were previously impossible to print. So far, several anti-reflective films like TiN, SiOxNy:H, and organic films for the high reflective substrate have been studied. In this paper, we suggest the novel anti-reflective structure for metal layer patterning, which is Al(aluminum)/SiO 2 stack structure. the reflectivity and the resist absorption rate are simulated for the I-line, and ArF lithography. The simulated thickness of ARL(Al) and ARL(SiO 2 ) for zero reflectivity on the wavelength of 365 nm was 12.6 nm and 95.2 nm respectively, and on the 193 nm was 20.4 nm and 98.8 nm. The process latitude according to the thickness variation of the deposited ARL(Al) and ARL(SiO 2 ) films, and the results of the lithography experiment were discussed.

We present a thorough analysis of physics-based hot-carrier degradation (HCD) models. We discuss the main features of HCD such as its strong localization at the drain side of the device, the weakening of the degradation at higher temperatures, and the change of the worst-case condition in small devices. The first feature is related to "hot" carriers, while the second is controlled by the fraction of "colder" particles. The latter feature is related to the change of the silicon-hydrogen bond-breakage mechanism from the single- to multiple-carrier process. All these findings suggest that the interface state creation process is controlled by the manner how the carriers are distributed over energy, that is, by the carrier energy distribution function. We distinguish between three main aspects of the physical picture behind hot-carrier degradation: carrier transport, microscopic mechanisms of defect creation and simulation of degraded devices. Therefore, we analyze and classify the existing HCD models in this context. Finally we present our hot-carrier degradation model based on a thorough evaluation of this distribution function by means of full-band Monte-Carlo device simulator. Our approach tries to address the whole hierarchy of physical phenomena in order to capture all the essential aspects of hot-carrier degradation.

Hot-carrier degradation is associated with the buildup of defects at or near the silicon/silicon dioxide interfaced of a metal-oxide-semiconductor transistor. However, the exact location of the defects, as well as their temporal buildup during stress, is rarely studied. In this work we directly compare the experimental interface state density profiles generated during hot-carrier stress with simulation results obtained by a hot-carrier degradation model. The developed model tries to capture the physical picture behind hot-carrier degradation in as much detail as feasible. The simulation framework includes a transport module, a module describing the microscopic mechanisms of defect generation, and a module responsible for the simulation of degraded devices. Due to the model complexity it is very important to perform a thorough check of the output data of each module before it is used as the input for the next module. In this context a comparison of the experimental interface state concentration observed by the charge-pumping technique with the simulated one is of great importance. Obtained results not only show a good agreement between experiment and theory but also allow us to draw some important conclusions. First, we demonstrate that the multiple-particle mechanism of Si–H bond breakage plays a significant role even in the case of a high-voltage device. Second, the absence of the lateral shift of the charge-pumping signal means that no bulk oxide charge buildup occurs. Finally, the peak of interface state density corresponds to the peak of the carrier acceleration integral and is markedly shifted from typical markers such as the maximum of the electric field or the carrier temperature. This is because the degradation is controlled by the carrier distribution function and simplified schemes of hot-carrier treatment (based on the mentioned quantities) fail to describe the matter.

Purpose : To report a case of surgical treatment of bilateral bullous exudative retinal detachment associated with Vogt-Koyanagi-Harada disease. Case summary: A 64-year-old woman presented with decreased visual acuity, headache, and hearing loss for 2 months. Visual acuity was hand motion in the right eye and light perception in the left eye. Intraocular pressure was 16 mmHg in the right eye and 24 mmHg in the left eye. Slit lamp examimation disclosed corneal edema, conjunctival ciliary injection with chemosis, rubeosis iridis, and posterior synechia in both eyes. Fundus examination demonstrated bilateral bullous exudative retinal detachment. Lumbar puncture revealed pleocytosis and auditory function test showed neurosensory hearing loss. She was diagnosed as having bilateral bullous exudative retinal detachment associated Vogt-Koyanagi-Harada disease. On hospital day 3, intravitreal triamcinolone injection with external subretinal fluid drainage was performed in the right eye and on hospital day 6, intravitreal triamcinolone injection with external subretinal fluid drainage was performed in the left eye. Two months later, best corrected visual acuity was 0.2 in the right eye and 0.04 in the left eye. Conclusions: Intravitreal trimacinolone acetonide injection with external subretinal fluid drainage is one of the good treatment for bullous exudative retinal detachment associated with Vogt-Koyanagi-Harada disease.