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Wirebonding process is one of the most challenging assembly manufacturing process in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to resolve the wire to die shorting on reverse stitch on ball (RSOB) and prevent irregular looping height for the substrate land grid array (LGA) device. Comprehensive parameter optimization was done particularly on the wirebond looping to ensure that no wire depression and no capillary hitting would occur wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the occurrence of looping issues during the lot process. For future works, the configuration and technique could be applied on packages with similar situation.

The continuing advances of die technology of integrated circuits (IC) miniaturization bringing more complexity in the product. At unusual conditions one may encounter new challenges intrinsic to the structure of the package. The study aims to qualify a product such as multi-stacked dice configurations with baseline reference using same die technology. The only difference is the substrate layout in which defined for the electrical purpose. The challenge is to understand and resolve low intermetallic coverage (IMC) on each die which may lead to manufacturability and reliability problems over time.

The integrity of the assembly wirebond process’ 2nd bond poses a big challenge for semiconductor manufacturing of quad-flat no-leads (QFN) devices, particularly on multiple wires on a lead. These devices are vulnerable to induce or obtain broken wire at heel defect. This type of defect is an abnormality in the formation of the stitch, mostly a crack or fracture seen on the facade of the stitch. Normally, it happens when there is too much vibration or transfer of ultrasonic generator (USG) power combined with high bonding force on 2nd bond. In the case of leads with common wires, broken wire at heel could also happen through excessive USG application resulting to transfer of resonance on adjacent wires. This paper presents a better understanding and analysis done to provide an adequate and appropriate solution to broken wire at heel issue.

Intermetallic coverage (IMC) is one of the critical wirebond output responses that is usually checked to ensure the ball to pad integrity. The success of wirebonding relies on the formation of an interfacial intermetallic growth of ball bond to ensure it can withstand reliability stresses. The challenging approach in IMC analysis detect as over-etching around IMC area that leads to inaccurate IMC data collection. To address the over-etching, we generate a new method which is backside polishing that results to a reliable IMC data collection and help reduced the cycle time of IMC data gathering.

With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents the modification and improvement done on the process plate design to eliminate the bouncing effect of the silicon die that leads to off-centered ball (OCB) reject during the formation of wire on a quad flat no-leads (QFN) device. The panel type single-row process plate cannot totally vacuum the warped leadframe and this is resulting to off-centered ball. Through changing the panel type single-row process plate to panel type multi-hole process will have a strong vacuum sucked underneath the leadframe and eliminates the occurrence of off-centered ball. Future works could use the improved process plate design for devices of similar configuration.

New devices and technologies in the semiconductor industry are getting more challenging to process because of inherent issues especially on quad-flat no-leads (QFN) packaging assembly. This paper is focused on the improvement done for QFN leadframe device to address the major machine assist during the lot processing at wirebond process. Illumination and visual of the leadframe and the sand blasting process plate on the machine are difficult to separately distinguish due to similar color shade of the materials, thus frequent machine assists ensued. To reduce the frequent machine assist occurrence, an improvement is done through enhancing the process plate by using a black chrome to totally separate the illumination of leadframe and the process plate. Ultimately, the machine assist during wirebonding process is improved (the longer the better) from 16 minutes to 6 hours continuous and uninterrupted running.

During new product development of a substrate land grid array (LGA) device, issues were encountered at wirebonding process due to design constraints. This paper is focused on addressing the wire-to-wire short defect during wirebonding process of the first bond. Wirebond process optimization was comprehensively employed, but eventually recommended to have a substrate redesign with relocated bond fingers to increase the wire angle (less steep) between the first bond and the second bond. With the improvement done in the substrate design and through wirebond process optimization, wire-to-wire short defect occurrence was successfully eliminated.

Wirebonding is one of the most challenging assembly manufacturing processes in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to mitigate misplaced ball issues and prevent pattern recognition alignment errors. Parameter optimization particularly on wirebond looping was done to ensure that the silicon die’s L-fiducial is visible and not obstructed by the wires, which is the operator point or die reference of the unit during wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the pattern recognition alignment error and misplaced ball issues during the lot process. For future works, the configuration and technique could be applied on packages with the similar situation.

The paper focused on the improvement done in quad-flat no-leads (QFN) leadframe package assembly to address the quantity of rejection of crumpled leadframe during handling at wirebond process station. Overload sensor at the output magazine handler was found out to be defective, hence a new sensor was installed. With the improvement done, crumpled leadframe strip occurrence was ultimately eliminated.

This paper presents the modification and improvement done on the wire clamp and top plate (WCTP) design to eliminate the bouncing effect of the silicon die that leads to smashed ball reject during the formation of wire. The protrusion of the unit on the vacuum hole produced movement and slight vibration that affects the consistency of wirebonding. Through changing the standard vacuum hole to micro-holes provides underneath support to the unit and eliminates the overhanging or protrusion during the formation of wire. The implementation of the micro-hole design reduced the defect parts per million (dppm) occurrence to zero.

This paper presents the application of an innovative design of wirebond process plate during wirebonding process of thin semiconductor carrier such as the pre-encapsulated leadframe. The implementation of the specialized process plate aims to improve the conventional method of wirebonding from panel type to single-row design to reduce the occurrence of warpage on thin leadframes. In this study, an 85% reduction for warpage level is achieved after the introduction of the new design of process plate. Future works could use the improved process plate design for devices of similar configuration.

With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents an improvement done in quad-flat no-leads (QFN) leadframe package to resolve the quantity of unit rejection due to leads scratch underneath the leadframe. Moreover, the reject manifestation was captured after wirebonding process. Parameter optimization particularly for the second bond with the combination of bond force and bond scrubbing parameters was done to totally eliminate this type of issue after wirebonding process. With the wirebonding process optimization and improvement done, a reduction of 95 percent of leads scratch occurrence was achieved.

New design for a certain issue in semiconductor industry is another way to modify the standard configuration into specified limit or to make a possible solution of the problem. This paper presents a new modified design for wirebond top plate with a bias platform structure that will maintain a consistent second bond into a leadframe leads with half-etch configuration on quad-flat no-leads (QFN) packages especially in wirebond process. This paper used a side by side comparison to proof that the new design is better than the older design. With the new specialized wire clamp and top plate design, parts per million (PPM) level performances is improved by almost 90%.

This technical paper presents a study of wirebond selection highlighting the package electrical modeling and simulation done for semiconductor integrated circuit (IC) leadframe package (hereinafter referred to as Device Z) with different wirebond configurations: Gold 2N 1.3 mil, Gold 4N 1.3 mil, Copper 1.3 mil, Copper 1.2 mil, Copper 1.1 mil and Copper 1.0 mil. Package design, modeling and simulation are essentially important in the early stage of the package development, particularly at the package feasibility phase. As Device Z is previously assembled with Gold 4N 1.3 mil wirebond configuration, this technical paper focused in determining the best alternative for Gold 4N 1.3 mil in wirebonding through package modeling and simulation. Statistical analysis reinforced the study to verify the trend and to check if there is significant statistical difference in the resistance, inductance and capacitance (hereinafter referred to as RLC) performance of the device given the different wirebond configurations. Cost analysis was crucial to determine the cost impact of using different wires. Prioritizing the wirebond thickness and cost without sacrificing the electrical performance, Copper 1.1 mil would be the most suitable replacement for Gold 4N 1.3 mil wirebond configuration. However, since Copper 1.1 mil is not yet available in the market, Copper 1.2 mil could be used, with better electrical parameters. In addition, Copper wire offered significant cost improvement over its Gold counterpart. Computed cost per unit of Copper 1.3 mil is just 6% of the total cost of the Gold 4N 1.3 mil – that is 94% cost savings. Ultimately, Copper wire technology offers significant cost savings and could pave the way for more businesses in the plant.

Quad-flat no-leads (QFN) is a type of leadframe device in semiconductor industry wherein the silicon chip or die is mounted on leadframe pad through a die attach glue or film.