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Molybdenum oxide is an efficient hole collector for silicon solar cells. However, its optoelectronic properties deteriorate during cell manufacturing. To assess this issue, the optoelectronic properties and microstructure of molybdenum oxide-based hole contacts are evaluated at different steps of the manufacturing process. Molybdenum oxide becomes more absorbing as it reduces when placed in contact with hydrogenated amorphous silicon, triggering the formation of a 2-nm thick SiOx layer, and when annealed after exposure to the plasma used to sputter the transparent conductive oxide. These changes in the contact properties result in a barrier that impedes hole transport when measuring I-V characteristics at room temperature. Nonetheless, cells still reach an efficiency of up to 20.7% when using a front metal electrode screen-printed at 210 degrees C (21.7% for reference cells). Above 60 degrees C, both molybdenum oxide-based and reference cells exhibit the same efficiency as this barrier to hole transport vanishes.

This contribution demonstrates an improved infrared response of the rear reflector of monofacial silicon heterojunction solar cells using aluminium-doped zinc oxide (AZO) in lieu of indium tin oxide (ITO) in the back electron-collecting shell. Along these lines, the carrier concentration and the thickness of the rear AZO layer are optimized in order to minimize the free-carrier and the plasmonic absorption losses without detrimentally affecting the selectivity and the electrical transport properties of the device. The respective reductions of free-carrier vs. plasmonic absorption losses are thoroughly analyzed. Furthermore, the open-circuit voltage and series resistance of the solar cells are shown to not be impacted by the AZO thickness and the carrier concentration within the investigated ranges. As a result of these optimizations, a significant decrease in the parasitic absorption is obtained, leading to a champion device with a short-circuit current density of up to 40.81 mA/cm2 and an efficiency of 23.96 %, featuring a standard screen-printed silver grid at the front with ca. 3.25% optical shadowing. In summary, AZO appears to be a promising indium-free alternative material to replace the back ITO commonly used in silicon heterojunction solar cells.

Carrier-selective passivating contacts have been demonstrated to be crucial to reach the practical efficiency limit of single junction, crystalline silicon (c-Si) based solar cells. Yet, the electrical transport losses affecting the collection of photogenerated carriers remain to be addressed. To this aim, different methodologies and characterization techniques are currently used. In this contribution, we propose the concept of shell as a new terminology to describe carrier-selective passivating contacts. Then, we present a novel characterization methodology using transfer length method (TLM) measurement under variable illumination to investigate the charge-carrier transport in amorphous/crystalline silicon heterojunction (SHJ) n-type contact stacks. We use technology computer-aided design simulation to model a TLM structure and to identify the physical phenomena and the key parameters affecting the contact resistivity ( ρ c ) and the charge carrier accumulation of such contact stacks. Then, the simulation results are compared with experimental data by performing variable-illumination TLM measurements of actual SHJ n-type contact stacks. Specifically, we demonstrate that illumination has a strong impact on the measured ρ c value, highlighting the importance of measuring ρ c under maximum power point conditions for a relevant characterization of solar cell transport losses. In addition, we investigate the dependence of ρ c to a change in the injected carrier density within the c-Si bulk to compare the illumination responses of different SHJ n-type contact stacks. In the quest for maximal efficiency, this method may insightfully complete other characterization techniques to further understand and study the electrical transport in solar cells.

Carrier collection in silicon heterojunction (SHJ) solar cells is usually achieved by doped amorphous silicon layers of a few nanometers, deposited at opposite sides of the crystalline silicon wafer. These layers are often defect-rich, resulting in modest doping efficiencies, parasitic optical absorption when applied at the front of solar cells, and high contact resistivities with the adjacent transparent electrodes. Their substitution by equally thin doped nanocrystalline silicon layers has often been argued to resolve these drawbacks. However, low-temperature deposition of highly crystalline doped layers of such thickness on amorphous surfaces demands sophisticated deposition engineering. In this paper, we review and discuss different strategies to facilitate the nucleation of nanocrystalline silicon layers and assess their compatibility with SHJ solar cell fabrication. We also implement the obtained layers into devices, yielding solar cells with fill factor values of over 79% and efficiencies of over 21.1%, clearly underlining the promise this material holds for SHJ solar cell applications.

Thin-film silicon layers deposited in parallel-plate PECVD reactors can be produced with varying microstructure, composition and properties, depending on deposition process conditions and on the underlying substrate properties. This allows for designing selective contacts well suited to limit recombination losses in wafer-based crystalline silicon solar cells. For such heterojunction selective contacts, we demonstrate that an hydrogenated amorphous silicon passivation layer with a high microstructure factor yields enhanced passivation, demonstrating > 30 ms carrier lifetime on 270 $\mu$m Fz wafer. Combining the developed intrinsic material together with doped layers with appropriate activation energy and defect density, we show silicon heterojunction solar cells with fill factor > 82 % and with certified efficiency up to 23.88 %. In addition, we report on PECVD process conditions impact on the functionality of back-contacted silicon heterojunction solar cells based on the innovative “tunnel-IBC” approach, which uses an advanced control and utilization of thin film silicon specific properties. A certified 24.42 % tunnel-IBC solar cell is reported, demonstrating the potential of this simple manufacturing approach for back-contacted devices. Advanced processing of thin film silicon layers is therefore demonstrated to enable for achieving high efficiency crystalline silicon devices.

Silicon heterojunction solar cells without metallization can be interconnected using SmartWire Connection Technology (SWCT). The module performances can be comparable to standard SWCT module and the electrical contact of wire to transparent conductive oxide (TCO) is stable during more than 200 thermo-cycles between -40°C to +85°C. Costs comparison shows that direct contact to TCO is still more expensive than standard SWCT using indium-tin coating. By switching to indium-free wire, the cost parity can be reached.

This paper reports on the development of an innovative back-contacted crystalline silicon solar cell with passivating contacts featuring an interband tunnel junction at its electron-collecting contacts. In this novel architecture, named “tunnel-IBC”, both the hole collector patterning and its alignment to the electron collector are eliminated, thus drastically simplifying the process flow. However, two prerequisites have to be fulfilled for such devices to work efficiently, namely (i) lossless carrier transport through the tunnel junction and (ii) low lateral conductance within the hole collector in order to avoid shunts with the neighboring electron-collecting regions. We meet these two contrasting requirements by exploiting the anisotropic and substrate-dependent growth mechanism of n- and p-type hydrogenated nano-crystalline silicon layers. We investigate the influence of the deposition temperature and the doping gas concentration on the structural and the selectivity properties of these layers. Eventually, tunnel-IBC devices integrating hydrogenated nano-crystalline silicon layers have been processed and demonstrate up to 23.9 % conversion efficiency.

We report on the fabrication of back-contacted silicon heterojunction solar cells with conversion efficiencies above 21%. Our process technology relies solely on simple and size-scalable patterning methods, with no high-temperature steps. Using in situ shadow masks, doped hydrogenated amorphous silicon layers are patterned into two interdigitated combs. Transparent conductive oxide and metal layers, forming the back electrodes, are patterned by hot melt inkjet printing. With this process, we obtain high short-circuit current densities close to 40 mA/cm $^{2}$ and open-circuit voltages exceeding 720 mV, leading to a conversion efficiency of 21.5%. However, moderate fill factor values limit our current device efficiencies. Unhindered carrier transport through both heterocontact layer stacks, as well as higher passivation quality over the minority carrier-injection range relevant for solar cell operation, are identified as key factors for improved fill factor values and device performance.

We examine damage-free transparent-electrode deposition to fabricate high-efficiency amorphous silicon/crystalline silicon heterojunction solar cells. Such solar cells usually feature sputtered transparent electrodes, the deposition of which may damage the layers underneath. Using atomic layer deposition, we insert thin protective films between the amorphous silicon layers and sputtered contacts and investigate their effect on device operation. We find that a 20-nm-thick protective layer suffices to preserve, unchanged, the amorphous silicon layers beneath. Insertion of such protective atomic-layer-deposited layers yields slightly higher internal voltages at low carrier injection levels. However, we identify the presence of a silicon oxide layer, formed during processing, between the amorphous silicon and the atomic-layer-deposited transparent electrode that acts as a barrier, impeding hole and electron collection.

Copper electroplating is investigated and compared with common silver printing techniques for the front metallization of silicon heterojunction solar cells. We achieve smaller feature sizes by electroplating, significantly reducing optical shadowing losses and improving cell efficiency by 0.4% absolute. A detailed investigation of series resistance contributions reveals that, at maximum power point, a significant part of the lateral charge-carrier transport occurs inside the crystalline bulk, rather than exclusively in the front transparent conductive oxide. This impacts optimization for the front-grid design. Using advanced electron microscopy, we study the inner structure of copper-plated fingers and their interfaces. Finally, a cell efficiency of 22.4% is demonstrated with copper-plated front metallization.

In recent years a significant amount of effort has been devoted towards the development of dopant-free carrier selective contacts for crystalline silicon (c-Si) solar cells. This short manuscript surveys a range of materials which have the potential to induce carrier-selectivity when applied to c-Si, including metals, metal oxides, alkali / alkaline earth metal salts, and organic conductors. Simple Ohmic test structures are used to assess the selectivity of these materials, that is, hole contacts are tested on p-type c-Si and electron contacts on n-type c-Si. Among these alternatives, a number of systems with exceptional potential are identified.

Hole and electron collectors in silicon heterojunction solar cells consist of hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Charge carrier extraction from these layers is achieved by electrodes consisting of a transparent conductive oxide and a metal layer. Earlier, the mere presence of the transparent conductive oxide layer on top of the hole collecting stack was shown to alter minority carrier lifetimes, at low minority injection levels, of the crystalline silicon absorber. In this work, we present a detailed investigation of the magnitude and nature of these effects and discuss their impact on silicon heterojunction solar cell performance for the different device architectures.

Silicon heterojunction (SHJ) technology enables high performance photovoltaics at acceptable cost. In this article, we show that this technology is also well suited for low to medium concentration applications. For this purpose, SHJ cells have been optimized and tested at different illumination levels and temperatures. An interesting increase of the efficiency temperature coefficient is observed with increasing illumination level. This behavior translates in improved performances of the tested SHJ devices under low to medium concentration applications, when operated at temperature above 25°C. This is linked to the behavior of the FF, exhibiting an improvement with increasing temperature while the cell is operated under high illumination level. This phenomenon suggests thermally assisted carrier transport through a barrier probably located at the TCO/p+ a-Si:H interface.

Silicon heterojunction solar cell technology (HJT) takes advantage of ultra-thin amorphous silicon layers deposited on both sides of monocrystalline silicon wafers, enabling excellent silicon wafer surface passivation resulting in high device power output and in addition to efficient use of thin wafers. A full cell processing platform was developed in our laboratory, enabling to achieve > 22 % cell efficiency. Advanced concepts for metallization and interconnection are under study, from fine-line printing combined with SmartWire interconnection to Copper plating. Importantly, we show that the HJT technology intrinsically enables high bifaciality of the cells (> 95 %), and further demonstrates a low thermal coefficient (< 0.2 – 0.3 %/°C). The high performance of heterojunction cells and SmartWire interconnection based modules allow for very low cost of electricity for Heterojunction based solar systems, with a potential below 6 Euro cents per kWh in Europe, bringing photovoltaics as a very competitive electricity source. It further provides upgrade potential towards 24 % cell efficiency.

A salient characteristic of solar cells is their ability to subject photo-generated electrons and holes to pathways of asymmetrical conductivity—‘assisting’ them towards their respective contacts. All commercially available crystalline silicon (c-Si) solar cells achieve this by making use of doping in either near-surface regions or overlying silicon-based films. Despite being commonplace, this approach is hindered by several optoelectronic losses and technological limitations specific to doped silicon. A progressive approach to circumvent these issues involves the replacement of doped-silicon contacts with alternative materials which can also form ‘carrier-selective’ interfaces on c-Si. Here we successfully develop and implement dopant-free electron and hole carrier-selective heterocontacts using alkali metal fluorides and metal oxides, respectively, in combination with passivating intrinsic amorphous silicon interlayers, resulting in power conversion efficiencies approaching 20%. Furthermore, the simplified architectures inherent to this approach allow cell fabrication in only seven low-temperature (≤200 ∘C), lithography-free steps. This is a marked improvement on conventional doped-silicon high-efficiency processes, and highlights potential improvements on both sides of the cost-to-performance ratio for c-Si photovoltaics. The use of doped-silicon contacts in silicon solar cells adds cost and complexity to the fabrication process. These issues can now be circumvented by using dopant-free carrier-selective interfaces on silicon, realized by alkali metal fluorides and metal oxides.

Low-temperature (

Microchannel plates are vacuum-based electron multipliers for particle--in particular, photon--detection, with applications ranging from image intensifiers to single-photon detectors. Their key strengths are large signal amplification, large active area, micrometric spatial resolution and picosecond temporal resolution. Here, we present the first microchannel plate made of hydrogenated amorphous silicon (a-Si:H) instead of lead glass. The breakthrough lies in the possibility of realizing amorphous silicon-based microchannel plates (AMCPs) on any kind of substrate. This achievement is based on mastering the deposition of an ultra-thick (80-120 μm) stress-controlled a-Si:H layer from the gas phase at temperatures of about 200 °C and micromachining the channels by dry etching. We fabricated AMCPs that are vertically integrated on metallic anodes of test structures, proving the feasibility of monolithic integration of, for instance, AMCPs on application-specific integrated circuits for signal processing. We show an electron multiplication factor exceeding 30 for an aspect ratio, namely channel length over aperture, of 12.5:1. This result was achieved for input photoelectron currents up to 100 pA, in the continuous illumination regime, which provides a first evidence of the a-Si:H effectiveness in replenishing the electrons dispensed in the multiplication process.

Excellent amorphous/crystalline silicon interface passivation is of extreme importance for high-efficiency silicon heterojunction solar cells. This can be obtained by inserting hydrogen-plasma treatments during deposition of the amorphous silicon passivation layers. Prolonged hydrogen-plasmas lead to film etching. We report on the defect creation induced by such treatments: A severe drop in interface-passivation quality is observed when films are etched to a thickness of less than 8 nm. Detailed characterization shows that this decay is due to persistent defects created at the crystalline silicon surface. Pristine interfaces are preserved when the post-etching film thickness exceeds 8 nm, yielding high quality interface passivation. (C) 2013 AIP Publishing LLC.

This paper reviews recent progress made at CSEM on the development of low-temperature processes for the fabrication of amorphous silicon-based passivated contacts and for the metallization of high-efficiency silicon heterojunction (SHJ) solar cells. Intrinsic a-Si:H passivation layers were optimized by trying to minimize the drop in lifetime usually observed after the deposition of the p-doped a-Si:H layer on top. State-of-the-art passivation levels are obtained, demonstrated by minority carrier lifetimes above 50 ms on lowly doped wafers, and close to 18 ms on actual SHJ cell precursors with buffer layers as thin as 4 nm. Regarding cell metallization, the screen-printing process of low-temperature Ag pastes has been optimized, resulting in finger width as low as 16 µm. Alternatively, a photolithography-free copper electroplating process has been developed. Using inkjet printing of hotmelt for patterning, 25-µm-wide and highly conductive fingers can be deposited. This process was tested in SHJ cell pilot production conditions, showing high cell performance (22.3% median efficiency) and good reproducibility. Finally, using the developed passivated contacts and screen-printing process, SHJ solar cells fabricated with industry-compatible processes showed efficiencies up to 23.1% on large-area devices and up to 23.9% on 4 cm2 devices.

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solar cells. Based on our findings, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.

Thin, light-absorbing films attenuate the Raman signal of underlying substrates. In this article, we exploit this phenomenon to develop a contactless thickness profiling method for thin films deposited on rough substrates. We demonstrate this technique by probing profiles of thin amorphous silicon stripes deposited on rough crystalline silicon surfaces, which is a structure exploited in high-efficiency silicon heterojunction solar cells. Our spatially-resolved Raman measurements enable the thickness mapping of amorphous silicon over the whole active area of test solar cells with very high precision; the thickness detection limit is well below 1 nm and the spatial resolution is down to 500 nm, limited only by the optical resolution. We also discuss the wider applicability of this technique for the characterization of thin layers prepared on Raman/photoluminescence-active substrates, as well as its use for single-layer counting in multilayer 2D materials such as graphene, MoS2 and WS2.

Transition metal oxides (TMOs) are commonly used in a wide spectrum of device applications, thanks to their interesting electronic, photochromic, and electrochromic properties. Their environmental sensitivity, exploited for gas and chemical sensors, is however undesirable for application in optoelectronic devices, where TMOs are used as charge injection or extraction layers. In this work, we first study the coloration of molybdenum and tungsten oxide layers, induced by thermal annealing, Ar plasma exposure, or transparent conducting oxide overlayer deposition, typically used in solar cell fabrication. We then propose a discoloration method based on an oxidizing CO2 plasma treatment, which allows for a complete bleaching of colored TMO films and prevents any subsequent recoloration during following cell processing steps. Then, we show that tungsten oxide is intrinsically more resilient to damage induced by Ar plasma exposure as compared to the commonly used molybdenum oxide. Finally, we show that parasitic absorption in TMO-based transparent electrodes, as used for semitransparent perovskite solar cells, silicon heterojunction solar cells, or perovskite/silicon tandem solar cells, can be drastically reduced by replacing molybdenum oxide with tungsten oxide and by applying a CO2 plasma pretreatment prior to the transparent conductive oxide overlayer deposition.

Substituting the doped amorphous silicon films at the front of silicon heterojunction solar cells with wide-bandgap transition metal oxides can mitigate parasitic light absorption losses. This was recently proven by replacing p-type amorphous silicon with molybdenum oxide films. In this article, we evidence that annealing above 130 degrees C-often needed for the curing of printed metal contacts-detrimentally impacts hole collection of such devices. We circumvent this issue by using electrodeposited copper front metallization and demonstrate a silicon heterojunction solar cell with molybdenum oxide hole collector, featuring a fill factor value higher than 80% and certified energy conversion efficiency of 22.5%. (C) 2015 AIP Publishing LLC.

Soiling is the major cause of power loss of photovoltaics (PV) and concentrated solar power (CSP) in desert areas. Electrodynamic cleaning system (EDS) is an automatic and water-free integrated cleaning system for mirrors or solar panels, which uses pulsed electric fields to remove dust off their surface. The first EDS field test over a long period on PV modules is reported here and shows a clear effect on soiling reduction in real conditions in Saudi Arabia. A total of 458 days of measurements is analyzed, and depending on the considered periods, performance losses due to soiling (soiling rate) can vary from -0.06%/day to -0.41%/day for a reference module, while the relative soiling rate reduction using an EDS can be up to 95.7% with an average of 32.1%. Cost calculations demonstrate an added value of the modules equipped with the EDS between 2.6 and 5.2 & xa2;/Wp compared with usual cleaning system, which is nearly between 10% and 20% of the module price. In addition, extended indoor tests of various electrode designs of EDS for heliostat dedicated to CSP or PV applications show a high cleaning efficiency of up to 98% with front glass thickness of more than 1 mm. A good specular reflectivity, only 4% lower than the bare reference mirror, is obtained with patterned sputtered silver in a spiral electrode design. High reliability of two types of electrode deposition is demonstrated after 200 cycles between -40 degrees C and +85 degrees C.