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Process sensitivity and variation, such as layer thicknesses, etch dimensions and doping levels are all process parameters that should be well understood when assessing their impact on end of process wafer quality and device performance. Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process- parameter variation understanding in earlier stages of technology development. A TCAD simulation was built and calibrated to match key electrical performance metrics of an experimental high performance SiGe HBT in 130nm BiCMOS technology, which was the device of focus in this study. Figure 1 includes a TCAD cross section of the device1. Neural net techniques, a machine-learning methodology, the development and deployment of which has grown significantly over the last three decades, is used to expand the scope of TCAD to process variability2-3.The aforementioned calibrated TCAD deck was used to generate training data for the neural network process compact model in place of hardware data. Key process features, as listed in table 1 were a few of the process conditions that were varied from nominal values to characterize the variation in resulting electrical performance. Figure 2 includes a 1D schematic view of the epitaxial layers of the HBT, highlighting some of the process features varied in simulation. The neural network was trained using a data analysis suite using three hidden layers with 16 neurons each to get a best fit to the training data input and output values. The foundation of this approach was a TCAD simulation calibrated to match performance of the nominal HBT device of focus. Key AC and Gummel performance parameters had good agreement with hardware data as illustrated in Figure 3a and b. Thousands of individual TCAD simulations with combinations of varied process feature values were then executed to generate neural network training data in lieu of hardware data- utilizing reported standard deviations of each process parameter. The trends and sensitivity of this data was then reflected in the process compact model, which would provide results for large-scale calculation and analysis. Beta was the electrical parameter of focus in this study, where its changes in process variation (mean and standard deviation) were predicted by the trained PCM. The agreement with hardware electrical parameter Beta with respect to Boron dose in Figure 4 demonstrates how use of calibrated TCAD as a basis can empower prediction of large-scale hardware results without the extent of hardware expense. Use of this tool can be extended to simulate and analyze larger populations than what would be feasible for hardware (in several thousands) to predict the effect of process input changes on uniformity of electrical parameters. Figure 5 demonstrates how the changes in standard deviation of Beta can be predicted as a function of Boron dose variation-through generation of large simulated populations by the PCM. The resulting work on a state-of-the-art SiGe BiCMOS technology demonstrates how specific simulation tools, like TCAD-trained process compact models can be leveraged for enhanced process understanding and improvement. The data generated from these tools can supplement or replace hardware and corresponding data, saving in development costs and associated hours in manpower. They can also enable earlier and more agile decision-making about key production metrics throughout the technology development process. Calibrated TCAD infrastructure, coupled with neural-net technology have potential to fulfill pivotal roles through the timelines of technology development, rather than just being utilized when a technology is mature. References: J. Pekarik et al., "A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications," 2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Coronado, CA, 2014, pp. 92-95. W. Coit, B.T. Jackson & A.E. Smith, “Static neural network process models: Considerations and case studies,” International Journal of Production Research, 1998, 36:11, pp. 2953-2967. Borges, T. Ma, W. Ng, S. Krishnamurthy and L. Bomholt, "Implementation of TCAD-for-Manufacturing Methodology using Process Compact Models," 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, 2006, pp. 1853-1856. Figure 1

Advanced BiCMOS technology is a cost-effective candidate for wide-range of applications, including Radar (automotive radars, high-speed industrial sensors), high-speed wireless and wireline communication, high-speed instrumentation, and mmWave THz imaging and sensing that require high performance SiGe HBTs with high cut-off frequencies fT and high maximum frequencies fMAX. Development of SiGe HBTs in BiCMOS technology with both high fT and fMAX faces significant challenges. Vertical scaling is employed to increase fT in advanced SiGe HBTs including reduction in base and collector thickness or by increasing the collector doping. All these approaches reduce the carrier transit times, but result in an increase in the base resistance and the collector-base capacitance, which degrade fMAX. To overcome these limits, lateral scaling is necessary to reduce the base resistance and the collector-base capacitance. Reduction in emitter width reduces the intrinsic base resistance and Ccb, self-aligned emitter-base integration schemes reduce the extrinsic base link resistance, and raised extrinsic base helps with lower Rb and Ccb. In short, these scaling rules and approaches would need to reduce both base resistance and collector-base capacitance simultaneously for improved fMAX and fT In this paper, results from two experimental studies are presented in a 90nm SiGe BiCMOS technology. Compared with the baseline, one experiment shows more reduction in collector-base capacitance, while the other shows more reduction in base resistance. Both experiments achieved 300GHz fT and met or exceeded the 360GHz fMAX goal of the technology. In addition to straight vertical and lateral scaling, a series of experiments employing other process techniques and structure innovation have also been studied and are reviewed in this paper, including millisecond anneal techniques, low temperature silicide and low temperature contact processes, and secondary trench isolation, achieving fT around 300GHz and fMAX toward half THz.

A 60-GHz band 2 × 2 phased-array transmitter implemented in 65-nm bulk CMOS is described. Two-dimensional beam steering in the azimuthal and elevation planes is implemented via LO phase shifting in a transmitter that also supports direct or IF up-conversion. Full current bleeding in the final upconversion mixer suppresses flicker noise, and dynamic LO biasing suppresses carrier feedthrough. The 2.9 × 1.4 mm2 chip consumes a total of 590 mW from a 1-V supply when driving all four channels at a maximum saturated output power of 11 dBm, with 20 dB gain per transmitter. Carrier leakage varies between - 20.5 dBc ±0.5 dB and sideband rejection is 25 to 28 dBc among the four transmitters when measured on the same die. The measured phase noise is 1.7 ± 1 dB higher than the theoretical 21.6 dB increase in the phase noise due to 12 X frequency multiplication of the injected LO. Maximum power-added efficiency of the transmit amplifier is greater than 16%, and gain is above 17 dB from 54 to 61 GHz.

A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and radial stubs for ac ground. Dummy-prefilled microstrip lines, with explicit yet efficient dummy modeling, are used as a compact, density-rule compliant matching element. Transistor layout with parallel gate feed yields 5.7 dB of MSG at 150 GHz. Measurement shows the amplifier exhibits 8.2 dB of gain, 6.3 dBm of Psat, 1.5 dBm of PidB and 27 GHz of 3 dB bandwidth, while consuming 25.5 mW at 1.1 V. The dummy-prefilled microstrip line exhibits QTL ? 12 up to 200 GHz.

An 80GHz bandwidth distributed amplifier with 7V pp differential output swing and P O1dB of 13 dBm per side, a 125GHz bandwidth PIN-diode SPST switch with 23dBm output compression point and over 22 dB of isolation up to 160 GHz, and a 40–100GHz bandpass filter with less than 3dB insertion loss are reported in a 90nm SiGe BiCMOS process. The circuits represent critical building blocks for analog transmitter or receiver front ends in next generation instrumentation and 100GBaud fiberoptic systems.

Peak f T of 660GHz is reported for HBT f T doubler designs in IBM 90nm SiGe BiCMOS technology 9HP. This high performance f T doubler utilizes a longer HBT for output stage compared to the input stage HBT (length ratio 2:1) resulting in improved transconductance and lower thermal resistance. The impact of HBT layout on the circuit performance and trade-off between thermal resistance and f T is also investigated. f T doubler circuit can be used as a single transistor in several circuit applications like A/D converters and broadband circuits where higher performance is desired.

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBM's large volume 200mm fabrication line. The technology features 300 GHz f T and 360 GHz f MAX high performance SiGe HBTs, 135 GHz f T and 2.5V BV CEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

A frequency-agile, low-power 3-5 GHz FM transceiver with on-chip calibration, and digital control of Rx gain, Tx power, and carrier frequency is described. The FCC-compliant transmitter incorporates a 3-phase CCO and frequency-tripling PA. A tunable LNA, envelope detector, limiter, and FSK demodulator comprise the receiver. Measured Rx sensitivity is -80.5 dBm (10 -3 BER) at 100 kb/s. The 0.9 mm 2 IC fabricated in 90 nm RF-CMOS dissipates 630 μW in Tx and 580 μW in Rx mode from a 1 V supply.

Impact of mutual thermal coupling on the performance of a single 90nm SiGe heterojunction bipolar transistor (HBT) due to the presence of power dissipating elements like other HBTs in near vicinity is presented in this paper. Mutual thermal resistance (Rth,mutual) has been computed as a function of spacing between the single HBT and a ring of HBTs surrounding the device. HBT structural design variations including device layout schemes, metal wire stack connected to the emitter, deep trench (DT) depth and emitter to DT spacing, for reduced self thermal resistance (Rth), have been explored in this paper. An updated thermal resistance model accounting for the heat flow through the metal wiring stack connected to the emitter is also reported.

High performance Schottky Barrier Diodes (SBDs) with cut-off frequency (fc) ~2.0 THz integrated into a 90nm SiGe BiCMOS technology for millimeter wave (mm-wave) applications are presented in this paper. To our knowledge, this is the highest reported fc for a SBD in a BiCMOS technology. The SBDs reported here have low reverse bias leakage with breakdown voltage of ~5V, and have been integrated in the base technology without the addition of any extra processing step. The affects of variation of critical process and device parameters - undoped silicon layer (n-epi) thickness, thermal cycle associated with deep-trench formation, cathode reach-through width, and anode area on device performance have also been investigated and are presented here.

Scaling both the fT and the fMAX of SiGe HBTs is quite challenging due to the opposing physical device requirements for improving these figures of merit. In this paper, millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. These processes when combined with a novel approach to address the collector-base capacitance are shown to produce high performance SiGe HBT devices which demonstrate operating frequencies of 300/420GHz fT/fMAX. This is the first report of 90nm SiGe BICMOS with an fMAX exceeding 400GHz.

Having two, or more, transistors with different values of f T and BV CEO provides flexibility to circuit designers in making tradeoffs of power and performance. The process complexity and resulting cost of fabricating these transistors on the same wafer is another important factor. Three different approaches for co-integrating high-performance and high-breakdown SiGe npn HBTs with minimal process deviation are presented herein. The work features a high-performance HBT with f T × BV CEO product of 500GHz-V and a high-breakdown HBT with over 430GHz-V integrated on the same wafer with one-mask deviation.

A broadband, frequency-selective low-noise amplifier (LNA) with at least 25 dB of rejection at frequencies below the L-band (includes GPS and GSM carriers) is fabricated in a 90 nm standard CMOS process. The proposed LNA can be used for broadband impulse-radio ultra-wideband (IR-UWB) and frequency modulated FM-UWB. The frequency-selective (3.5–10.5 GHz) LNA is power-to-current (P-I) configured and comprises nested reactive feedback loops: a positive current-to-current (I-I) feedback loop to boost the power gain and a negative I-I feedback loop for impedance and noise matching. The measured gain of the P-I LNA is 15±3 dB. It has a noise figure (NF) of 2.4±0.8 dB and a 1-dB gain compression point (P −½dB ) of −17.5±2.5 dBm. The die area of the LNA is 0.7×0.8 mm2 and it consumes 9.6 mW from a 0.8 V power supply. The proposed P-I LNA is most suitable for a sub-1 V single-cell radios.

In this paper, we discuss a novel technique to reduce base resistance (R b ) and collector-base capacitance (C cb ) for higher F max in high-speed SiGe HBTs. In order to reduce C cb , we first located the origins of the different components of C cb through AC extraction. Then we utilized scanning capacitance measurements (SCM) to examine the shape of the collector-base depletion. We then propose a method to reduce the extrinsic C cb , namely by using reticle enhancement techniques to print a blocking oxide layer to inhibit boron outdiffusion. An additional benefit was the reduction of R b by reducing the base link resistance.

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

Mm-wave digitally-controlled oscillators (DCOs) with reconfigurable passive resonators are proposed, which achieve wide tuning range (>10%) and fine frequency resolution (9.7% linear tuning range and phase noise lower than −90.5 dBc/Hz at 1-MHz offset across the 56–62 GHz range. The T-DCO achieves fine frequency tuning step of 2.5 MHz, whereas that of the L-DCO is better than 160 kHz. The L-DCO and T-DCO consume 10 mA and 12 mA, respectively, from a 1.2-V supply. The core size of each DCO is 0.4×0.4 mm2.

In this paper, we investigate the emitter resistance R e in SiGe HBTs with speeds up to 280GHz, using a U-shaped polysilicon emitter. We observed that R e increased with lateral scaling, thereby degrading f T . Although a negligible component in the past, in this experiment R e * C cb transit time delay is playing a more significant role in limiting f T . R e was modeled to explain the increase due to lateral scaling, and was shown to result from the plugging of the emitter opening by the emitter polysilicon. Furthermore, process experiments were conducted to investigate the effect of emitter polysilicon thickness, sidewall height, and emitter i-layer thickness.

A millimeter wave (MMW) on-chip passive frequency-dependent inductor is described with different designed inductance values targeted at different frequency ranges using one device. The proposed frequency-dependent inductor design allows the optimization of multi-band impedance matching for MMW analog circuit designs with a single all-passive on-chip device. This device uses low-loss natural capacitors and multiple capacitively loaded ground return lines to provide MMW frequency-dependent effective device inductance. No on-chip switches are required in the proposed inductor design and it can allow circuit size reduction by allowing a single inductor to target different frequency ranges. Simulated inductance values in a 130 nm BiCMOS technology show a 61% change in inductance is possible between two frequency ranges: f 48 GHz. The proposed frequency-dependent inductor design has also been designed and measured in a 45 nm CMOS process. Measured results show that the use of multiple capacitively loaded ground return lines is effective in creating an on-chip MMW frequency-dependent inductor.

In wireless receivers, large dynamic range (DR) input signals necessitate additional power consumption in baseband active filters. A 5th order Chebychev, ladder type, companding SC low-pass filter is described in this paper which provides gain switching based on the instantaneous value of the signal to handle peak-to-average-power ratio (PAPR), thereby reducing power dissipation for a given DR. Companding compresses the high DR input signal, processes it in a lower DR system (the filter in our case) and then expands the signal at the output [1]. Companding is an alternative to AGC, which sets the filter internal gains during the preamble/midamble so that the signal level in the filter is optimal to provide the minimum SNDR required by the specifications. The IEEE 802.11a/g WLAN receiver [2] presents 2 limitations to the use of AGC. First, the standard puts a stringent AGC settling time requirement (≪5.6µs). Since the filter needs extra settling time, AGC is implemented after the filter and before the ADC in the receiver baseband. Secondly, the high PAPR of OFDM signals requires headroom of at least 12dB in the DR of the filter. While dynamic impedance and gain scaling techniques have been proposed in the past as an alternative to AGC [3], this work addresses the PAPR problem.

A 4–4.5 GHz receiver front-end consisting of a 35 dB voltage gain regenerative amplifier, ultra-narrowband RF filter and an envelope detector demodulator for FM-UWB communication is described in this paper. Implemented in 65 nm CMOS, the measured receiver sensitivity is −83 dBm at 100 kbps data rate with 15 dB output SNR (10−6 BER). The 0.3 mm2 test chip includes a 50 Ohm buffer amplifier to facilitate testing and consumes 2.2 mW (excluding buffer) from a 1 V supply.

In this work a highly integrated, ultra-low-power BPSK receiver for short-range wireless communications is presented. The receiver consists of a power divider, two injection-locked RC oscillators with limiting buffers and an XOR output stage. The demodulation principle is based on the dynamic phase response of the two BPSK signal injected oscillators. As proof of concept, a 300 MHz receiver was implemented in a 90nm CMOS technology. The whole receiver has an active die area of 0.04 mm2, a sensitivity of −34 dBm at 1Mbps and consumes only 120 µW from 1V supply, which relates to an energy per bit of only 0.12 nJ/bit, a value which is among the best reported up-to-date for low-transmission rate systems.

A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10Mbps for the 0.35mm2 testchip in 90nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5mW at 0.8V, or 250pJ/bit.

Sub-1V supplies limit the output voltage swing and saturated output power of an amplifier integrated in deep-submicron CMOS technology. Aside from absolute output power, power-added efficiency (PAE), stability and gain are also important power-amplifier (PA) design considerations. High reverse isolation between output and input is necessary to mitigate the effects of antenna mismatch, limit unwanted interference between circuit blocks on-chip and to promote stability. Efficiency of the PA is also paramount for portable consumer electronic applications operating from a battery, such as short-range Gb/s communication SoCs operating in the unlicensed bands around 60GHz. Aside from the 60GHz band, long-range collision-avoidance radar for automobiles (77/79GHz), and radio imaging (94GHz) are also potential applications for CMOS at mm-wave frequencies [1–4].

Custom designed for the IEEE802.15.4a standard, a 2-stage pseudo-differential low-noise amplifier (LNA) with a notch ges 20 dB in the IEEE802.11a WLAN band is presented for impulse-radio ultra-wideband (ir-UWB). This band-reject LNA is power-to-current (PI) configured employing reactive dual-loop negative feedback, which reduces the noise figure and allows for orthogonal impedance and noise matching over the prescribed bandwidth (i.e., 3.25-10.25 GHz). The LNA is fabricated in 0.13 mum CMOS and presents a maximum power gain of 17 dB, a -9 dBm IIP3 and a 2.5 dB noise figure at 6 GHz, when matched to 50 Omega (single-ended). Noise figure variation across the pass-band(s) is limited to les 0.75 dB. Employing a current-reuse technique limits the total power consumption to les 15 mW from a 1.2 V supply. The LNA occupies a die area of 1.4 times 1.2 mm2.

An RF passive orthonormal ladder filter using transformers is presented, where the output is obtained from a linear, weighted combination of the voltages or currents at predetermined nodes or branches. With this topology, arbitrary rational transfer functions can be mapped onto silicon. Key features of this single-input, multiple-output (SIMO) topology include low-pass to band-pass/reject transformation without doubling the order of the filter and the realization of transmission zeros in the right-half-plane (RHP) (for superior approximations). As a proof of concept, a 7th order transformer-C filter implemented in CMOS 0.13 mum technology that can be used as a pulse shaping network (pulse width less than 0.5 ns) or band selection filter (offering a minimum of 20 dB attenuation at the IEEE802.11a WLAN band) for UWB transceivers is presented.

This paper presents an LC-tuned, 24-GHz single-pole double-throw (SPDT) transmit/receive (T/R) switch implemented in 90-nm CMOS. The design focuses on the techniques to increase the power handling capability in the transmit (Tx) mode under 1.2-V operation. The switch achieves a measured P-1dB of 28.7 dBm, which represents the highest linearity, reported to date, for CMOS millimeter-wave T/R switches. The transmit and receive (Rx) branches employ different switch topologies to minimize the power leakage into the Rx path during Tx mode, and hence improve the linearity. To accommodate large signal swing, AC floating bias is applied using large bias resistors to all terminals of the switch devices. Triple-well devices are utilized to effectively float the substrate terminals. The switch uses a single 1.2-V digital control signal for T/R mode selection and for source/drain bias. The measured insertion loss is 3.5 dB and return loss is better than -10 dB at 24 GHz.

This paper describes a 60 GHz-band (output) frequency tripler with I/Q outputs implemented in a production 90 nm CMOS technology . Differential quadrature outputs with high phase accuracy and low amplitude error are required for single-sideband frequency translation. Regenerative peaking reduces power consumption and optimizes the response of the 50 Omega output buffer. The tripler can relax requirements on the design of the PLL synthesizer, as a fundamental (i.e., 60GHz) VCO and high-speed dividers, which may consume more power and compromise performance, are not required. It should be noted that the tripler operating frequency can be selected to fit the desired transceiver architecture and frequency plan.

There are strong reasons not to consider silicon technologies for mm-wave applications. Silicon comes up short in many comparisons to III-V semiconductors. Silicon carrier mobility is relatively low and so device-level FOMs of raw performance appear to be inferior. The silicon bandgap is relatively small and so voltage tolerance tends to be lower. Furthermore, highly-resistive or semi-insulating silicon substrates are difficult to achieve resulting in poorer isolation and higher losses in interconnects and passive devices. Each of these presents serious challenges to implementing mmwave functions. However, advances in silicon technology driven by high-performance digital applications, offer advantages to the mm-wave designer that might not be apparent on first consideration. Performance, quantified by fT , fmax orNFmin for example, has dramatically increased with geometry scaling and technology enhancements in both CMOS and SiGe HBTs [1]. Both CMOS and BiCMOS technologies have been used to demonstrate circuit functioning at frequencies in and above the K-band. Now, these silicon technologies are, by virtue of nanometer-scale design rules, able to implement staggering amounts of digital logic in a given area thereby enabling the on-chip integration of sophisticated control logic for performance tuning and/or digital signal processing. Furthermore, the worldwide manufacturing capacity of silicon technologies driven by consumer applications like gaming and personal electronic appliances assures low-cost. This will certainly provide an impetus for the evolution of mm-wave consumer applications. The combination of mm-scale wavelengths, low cost and the ability to integrate begs the consideration of array-based transceiver topologies being implemented on a single die or package.

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

We present extensive simulations of distortion in common-gate configured FETs, operated around Vds=0 V, using the new PSP MOSFET model Results are compared to measurements. We show that as a FET is configured into an increasingly more realistic circuit, that the PSP model's distortion performance improves correspondingly and that it can predict intermodulation distortion within ~3dB of measured data. Third, we quantify, for the first time, to what extent the intermodulation distortion, as represented by IIP3, can be improved by increasing the gate length (L) while scaling the width (W) to maintain the same Rds for constant insertion loss. We show that the magnitude of the 3rd derivative and IIP3 level off quickly with increasing L.

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fT's of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.