Search

In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as "no cycle stealing" at synchronous and asynchronous domain interfaces in macro synthesis, unit and chip timing are essential. Standard cell library characterization, for multi-power and timing challenges due to an additional delay for level translator circuitry, demand careful implementation in a high-speed synthesis methodology. We propose a pseudo algorithm and methodology for synthesis and timing that will correctly identify synchronous and asynchronous interfaces. Our proposed methodology shows how these interface paths should be excluded from "cycle stealing" and yet, take full advantage of slack borrowing for the rest of the design. We find ~28% and ~80% timing path improvement in two of the units for IBM's Power8TM (P8) microprocessor. As an alternative to high-effort custom design, we develop a synthesis-based physical design methodology that incorporates the use of a level translator, enabling designers to address major issues that encompass dual-voltage solutions in high-speed design. We find ~50% physical design effort savings using this methodology. P8 is a 12-core, 649 mm2, 4.2B transistor chip fabricated in IBM's 22-nm Silicon On Insulator (SOI) technology, which is fully functional to support a wide range of high performing systems with an operating frequency greater than 4.5GHz.

The two chips at the heart of the IBM z13™ system include a processor chip (referred to as the CP or Central Processor chip) and an L4 (Level 4) cache chip (referred to as the SC or System Controller chip), each 678 mm2 in area. The CP and SC chips were implemented with approximately 4 billion (4 × 109) and 7.1 billion transistors, respectively, in IBM's 22-nm SOI (silicon-on-insulator) technology, supporting eDRAM (embedded dynamic random access memory), and with up to 17 levels of metal available. In this paper, we discuss aspects of the circuit and physical design of these chips, including both digital logic and custom array implementation. In addition, we describe the design analysis methodology, along with some of the checks needed to ensure a robust, reliable, and high-frequency product.