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In this Letter, we experimentally investigate the impact of gate geometry on forward operation of Schottky-gate p-GaN high electron mobility transistors (HEMTs). In particular, we analyze devices with changing gate-metal/p-GaN junction area and p-GaN/AlGaN/GaN heterostructure area in the linear regime. These devices exhibit unique threshold voltage and subthreshold swing scaling dependence with gate geometry that is in contrast with classic field-effect transistors. On the other hand, peak transconductance and ON resistance are found to scale classically. We find that these results arise from the fact that with a Schottky contact to the p-GaN layer, under steady-state conditions, the p-GaN layer voltage is set by current continuity across the gate stack. Furthermore, a detailed scaling study of the gate current reveals that current flow across the p-GaN/AlGaN/GaN heterostructure is not uniform—instead, it preferentially flows through the ungated portion of the p-GaN layer. Our study concludes that in Schottky-type p-GaN gate HEMTs, the respective areas of two junctions constitute an additional design degree of freedom to fine-tune device performance.

We investigate time-dependent dielectric breakdown (TDDB) in AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) under forward bias AC stress which better emulates real-world operational conditions. To this end, we have performed TDDB experiments across a wide range of frequencies, temperatures, and recovery voltage levels. We find that TDDB under AC stress shows longer breakdown times than under DC stress and that this increase is more prominent with higher frequency, lower temperature, and more negative recovery voltage. We hypothesize that this is due to the dynamics of the gate stack in GaN MIS-HEMTs biased with a high positive gate voltage. Under these conditions, a second electron channel forms at the dielectric/AlGaN interface. This process is relatively slow as these electrons come from the 2DEG at the AlGaN/GaN interface and must overcome the energy barrier presented by the AlGaN. At the same gate voltage then, the electric field across the gate oxide is lower in magnitude under AC stress at high enough frequency than under DC stress explaining the obtained results.

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates.

The two-dimensional spatial distribution of structural degradation of AlGaN/GaN high electron mobility transistors was investigated under high-power electrical stressing using atomic force and scanning electron microscopy. It was found that pits form on the surface of the GaN cap layer at the edges of the gate fingers in the middle of the device. The average pit area and density increase gradually from the edge to the center of the fingers and are more common along inner fingers than fingers. It was also found that pit formation and growth are thermally activated., United States. Defense Advanced Research Projects Agency (ARL Contract W911QX-05-C-0087), United States. Office of Naval Research. Multidisciplinary University Research Initiative (Grant N00014-08-1-0655)

We have investigated the surface morphology of electrically stressed AlGaN/GaN high electron mobility transistors using atomic force microscopy and scanning electron microscopy after removing the gate metallization by chemical etching. Changes in surface morphology were correlated with degradation in electrical characteristics. Linear grooves formed along the gate edges in the GaN cap layer for all electrically stressed devices. Beyond a critical voltage that corresponds to a sharp increase in the gate leakage current, pits formed on the surface at the gate edges. The density and size of the pits increase with stress voltage and time and correlate with degradation in the drain current and current collapse. We believe that high mechanical stress in the AlGaN layer due to high-voltage stressing is relieved by the formation of these defects which act as paths for gate leakage current and result in electron trapping and degradation in the transport properties of the channel underneath., United States. Office of Naval Research (Grant number N00014-08-1-0655), United States. Army Research Laboratory (Contract Number W911QX-05-C-0087)

In this work, we investigate the time evolution of electrical degradation of GaN high electron mobility transistors under high voltage stress in the OFF state. We found that the gate current starts to degrade first, followed by degradation in current collapse and eventually permanent degradation in I[subscript D]. We also found that the time evolution of gate current degradation is unaffected by temperature, while drain current degradation is thermally accelerated.

We have investigated the surface morphology of electrically stressed AlGaN/GaN high electron mobility transistors using atomic force microscopy and scanning electron microscopy after removing the gate metallization by chemical etching. Changes in surface morphology were correlated with degradation in electrical characteristics. Linear grooves formed along the gate edges in the GaN cap layer for all electrically stressed devices. Beyond a critical voltage that corresponds to a sharp increase in the gate leakage current, pits formed on the surface at the gate edges. The density and size of the pits increase with stress voltage and time and correlate with degradation in the drain current and current collapse. We believe that high mechanical stress in the AlGaN layer due to high-voltage stressing is relieved by the formation of these defects which act as paths for gate leakage current and result in electron trapping and degradation in the transport properties of the channel underneath., United States. Office of Naval Research (Grant number N00014-08-1-0655), United States. Army Research Laboratory (Contract Number W911QX-05-C-0087)

We have developed a versatile methodology to systematically investigate the RF reliability of GaN High-Electron Mobility Transistors. Our technique utilizes RF and DC figures of merit to diagnose the degradation of RF stressed devices in real time. We have found that there is good correlation between selected RF and DC figures of merit. However, compared with DC stress, RF stress at the same bias point is found to be more severe and to introduce new degradation modes. At high power level, RF stress induces a prominent trapping-related increase in the source resistance most likely as a result of the creation of new traps. This is in contrast with drain degradation that often occurs under similar DC conditions. Our findings cast a doubt over the ability of DC life test in evaluating reliability under RF power conditions., U.S. Army Research Laboratory (DARPA-WBGS program), United States. Office of Naval Research (DRIFT-MURI program)

In GaN high-electron-mobility transistors, electrical degradation due to high-voltage stress is characterized by a critical voltage at which irreversible degradation starts to take place. Separately, cross-sectional TEM analysis has revealed significant crystallographic damage for severely degraded devices. Furthermore a close correlation between the degree of drain current degradation and material degradation has been reported. However, the role of the critical voltage in physical degradation has not been explored. In this work, we investigate the connection between electrical degradation that occurs around and beyond the critical voltage and the formation of crystallographic defects through detailed electrical and TEM analysis, respectively. We find that a groove in the GaN cap starts to be generated around the critical voltage. At higher voltages, a pit develops that penetrates into the AlGaN barrier. The size of the pit increases with stress voltage. We also observe a good correlation between electrical and material degradation., Pub. in Microelectronics Reliability, p1-6, 2010.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Cataloged from PDF version of thesis., Includes bibliographical references (p. 147-153)., The deployment of GaN high electron mobility transistors (HEMT) in RF power applications is currently bottlenecked by their limited reliability. Obtaining the required reliability is a difficult issue due to the high voltage of operation. In order to improve reliability, it is essential to develop detailed physical understanding of the fundamental degradation mechanisms. In this thesis, we investigate the physical mechanisms behind the electrical degradation of GaN HEMTs by performing systematic stress experiments on devices provided by our industrial collaborators. These devices are electrically stressed under various bias conditions while regularly characterized by a benign characterization suite. We observe that electrical stress beyond a critical voltage results in an increase in drain resistance, a decrease in maximum drain current, and a sharp increase in reverse gate current. We show that this mode of degradation is driven by electric field and that current is less relevant. Behind this degradation is trap formation that occurs at the critical voltage. To understand this, we have developed a new trap-analysis methodology. It is found that under stress, the density of traps increases in the AlGaN barrier layer in the proximity to the gate edge on the drain side of the device. We show that this degradation is enhanced under mechanical uniaxial tensile strain that is externally applied to the device. From our experiments, we propose a degradation mechanism of defect formation through the inverse piezoelectric. In this mechanism, high vertical electric field at the gate edge under high voltage increases tensile stress in the AlGaN layer due to piezoelectricity of the material., (cont.) When the elastic energy in the crystal exceeds a critical value, crystallographic defects are formed. These defects trap electrons and reduce drain current as well as provide leakage paths and increase gate current. We theoretically validate the plausibility of this hypothesis and provide a model for the critical voltage that agrees with experimental observations. Unlike conventional wisdom, hot electrons do not appear to be the direct cause of electrical degradation in the devices that we study. Our studies suggest several possibilities to improving the electrical reliability of GaN HEMTs., by Jungwoo Joh., Ph.D.

We have found that there is a critical drain-to-gate voltage beyond which GaN high-electron mobility transistors start to degrade in electrical-stress experiments. The critical voltage depends on the detailed voltage biasing of the device during electrical stress. It is higher in the OFF state and high-power state than at VDS = 0. In addition, as |VGS| increases, the critical voltage decreases. We have also found that the stress current does not affect the critical voltage although soft degradation at low voltages takes place at high stress currents. All of our findings are consistent with a degradation mechanism based on crystallographic-defect formation due to the inverse piezoelectric effect. Hot-electron-based mechanisms seem to be in contradiction with our experimental results., United States. Army Research Laboratory (Contract W911QX-05-C-0087)

In this paper, a simple and reliable method to estimate the channel temperature of GaN high-electron mobility transistors (HEMTs) is proposed. The technique is based on electrical measurements of performance-related figures of merit (I [subscript Dmax] and R [subscript ON]) with a synchronized pulsed I -V setup. As our technique involves only electrical measurement, no special design in device geometry is required, and packaged devices can be measured. We apply this technique to different device structures and validate its sensitivity and robustness., United States Army Research Laboratory (Contract W911QX-05-C-0087)

We used depth-resolved microcathodoluminescence spectroscopy (DRCLS) and Kelvin probe force microscopy (KPFM) to measure and map the temperature distribution and defect generation inside state-of-the-art AlGaN/GaN-based high electron mobility transistors (HEMTs) on a scale of tens of nanometers during device operation. DRCLS measurements of near band edge energies across the HEMT’s source-gate-drain regions reveal monotonic temperature increases across the submicron gate-drain channel, peaking under the drain side of the gate. DRCLS defect emissions mapped laterally and localized depthwise near the two-dimensional electron gas interface increase with device operation under the drain-side gate and correlate with higher KPFM surface potential maps., United States. Office of Naval Research (Grant N00014-08-1-0655)

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007., Includes bibliographical references (p. 83-85)., In spite of their extraordinary performance, GaN high electron mobility transistors (HEMT) have still limited reliability. In RF power applications, GaN HEMTs operate at high voltage where good reliability is essential. However, physical understanding of the fundamental reliability mechanisms of GaN HEMTs is still lacking today. In this thesis, we carry out systematic reliability experiments on industrial GaN HEMTs provided by our collaborators, TriQuint Semiconductor and BAE systems. In our study, GaN HEMTs have been electrically stressed at various bias conditions while they are being characterized by a benign characterization suite. We have confirmed that electrical stress on devices results in an increase in drain resistance RD and a decrease in maximum drain current IDmax. During the stress, traps are found to be generated. We have seen that this degradation is driven mostly by electric field, and current is less relevant to electrical degradation., (cont.) From a set of our experiments, we have hypothesized that the main mechanism behind device degradation is defect formation through the inverse piezoelectric effect and subsequent electron trapping. Unlike current conventional wisdom, hot electrons are less likely to be the direct cause of electrical degradation in the devices that we have studied. Our studies suggest a number of possibilities to improve the electrical reliability of GaN HEMTs., by Jungwoo Joh., S.M.