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Grain boundaries between 60° rotated and twinned crystals constitute the dominant type of extended line defects in two-dimensional transition metal dichalcogenides (2D MX2) when grown on a single c...

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.

Frequency-dependent I/Q imbalance and frequency-independent I/Q imbalance are the major impairments in wideband zero-IF receivers, and they both cannot be ignored. In this paper, a blind calibration model is designed for compensating these I/Q imbalances. In order to accurately estimate the imbalance parameters with low cost, a classification rule is proposed according to the frequency-domain statistical characteristics of the received signal. The calibration points in the frequency-domain are divided into two groups. Then, the amplitude imbalance and the frequency-dependent phase imbalance are derived from the group of signal points and, separately, the frequency-independent phase imbalance is calculated from the group of noise points. In the derivation of the frequency-dependent phase imbalance, a general fitting model suitable for all signal points is proposed, which does not require special calculations for either DC point or fs/2 point. Then, a finite impulse response (FIR) real-valued filter is designed to correct the impairments of received signal. The performances of the proposed calibration model are evaluated through both simulations and experiments. The simulation results show the image rejection ratio (IRR) improvement to around 35&ndash, 45 dBc at high signal-to-noise ratio (SNR). Based on the mismatched data of the ADRV9009 evaluation board, the experimental results exhibit the IRR improvement of both multi-tone and wideband signals to about 30 dBc.

This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core chip results in a gain of 9.0 dB and an output P1dB of –3 dBm. In the transmitting mode, the gain and output P1dB are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°. The power consumption is 150 mW in both work modes. The measured results show that the operating bandwidth, power consumption, gain, rms attenuation error and phase error have been significantly improved compared with the previous reports.

In this paper, Total Ionizing Dose (TID) and Single Event Burnout (SEB) effects are investigated on self-developed power VDMOS devices with breakdown voltage (BV) of 200 V. Different inter layer dielectrics (ILD) including Borophosphosilicate glass (BPSG) and Si3N4, and different passivation layers including Si3N4 and SiO2 are tested to evaluate their radiation hardness. The TID results indicate that the threshold voltage VTH of VDMOS is negatively shifted after radiation, and can barely be recovered by post TID annealing. As an ILD layer, Si3N4 is proved to be better than BPSG with less VTH shift. Passivation layer can also influence the TID hardness, which increases with the layer thickness. Heavy ion radiation tests indicate that the devices with different ILD and passivation designs can barely influence the SEB effects. All tested devices with normal breakdown voltage of 200 V cannot survive at VDS more than 80 V under heavy ion radiation.

The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V.

In this paper, a new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs (Monolithic microwave integrated circuit) is proposed. Based on the meshing criterion, an equivalent thermal model of GaAs PHEMTs with remarkably reduced mesh complexity is established, and the simplification of both layout pattern and vias of MMICs are performed. Theoretical analysis is applied for the calibration of the equivalent thermal model. Assisted by the meshing criterion, chip-level simulators are capable to obtain the peak temperature of MMICs without using averaging approximations, and achieve considerably high simulation accuracy. As examples, two MMIC power amplifiers are designed and implemented using GaAs PHEMT process. Thermal simulation and measurement results obtained with ANSYS ICEPAK and infrared thermography, respectively, show high consistency. The proposed meshing criterion can be applied to improve the accuracy of thermal analysis of MMICs, and the obtained precise peak temperature can be used to effectively assess the power threshold of the designed amplifiers in reliability tests.

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

This paper presents a high-efficiency continuous class B power amplifier MMIC (Monolithic Microwave Integrated Circuit) from 8 GHz to 10.5 GHz, fabricated with 0.25 &mu, m GaN-on-SiC technology. The Pedro load-line method was performed to calculate the optimum load of the GaN field-effect transistor (FET) for efficiency enhancement. Optimized by an output second-harmonic tuned network, fundamental to second-harmonic impedance, mapping was established point-to-point within a broad frequency band, which approached the classic continuous class B mode with an expanded high-efficiency bandwidth. Moreover, the contribution to the output capacitance of the FET was introduced into the output second-harmonic tuned network, which simplified the structure of the output matching network. Assisted by the second-harmonic source-pull technique, the input second-harmonic tuned network was optimized to improve the efficiency of the power amplifier over the operation band. The measurement results showed 51&ndash, 59% PAE (Power Added Efficiency) and 19.8&ndash, 21.2 dB power gain with a saturated power of 40.8&ndash, 42.2 dBm from 8 GHz to 10.5 GHz. The size of the chip was 3.2 &times, 2.4 mm2.

InGaAs nMOSFETs with Al2O3 and HfO2 as dielectric are analyzed. The devices with Al 2O3 show a slightly better subthreshold slope. Both high- $\kappa$ 's have an equal transconductance frequency dispersion $(g_{m}\mbox{-}f)$ . A reduction of $g_{m}\mbox{-}f$ is reached by scaling the HfO2 thickness. Positive gate stress leads to an increase in threshold voltage and subthreshold slope for all oxides. DC- $g_{\max}$ degradation is related purely to creation or activation of additional border traps during stress. The RF- $g_{\max}$ is not degraded. Similar time constants hint to a relation between the (semi-)stable degradation of DC- $g_{\max}$ and the threshold voltage increase. For the samples with HfO2, the effects of gate-stress induced additional border traps can only be detected at low frequencies. The created or activated defects are most likely located deep in the oxide. For Al2O3, the effect of additional border traps is also measurable at higher frequencies. The defects are created both closer to the Al2O3/InGaAs interface and deeper in the oxide.

In this article, the design and test of both a K-band dual-mode bandpass filter BPF pair and a K-band triple-mode BPF are presented based on N-mode temporal coupled-mode theory CMT. The expressions of transmission and reflection responses are analytically derived. All the parameters in the expressions have clear physical meanings and are easily optimized to reach the required filter performance. Aided by eigenmode simulations, concrete structures of the three integrated BPFs are designed and optimized to approach the calculated physical parameters. After the fabrications and measurements of the three BPFs, extended upper/lower stopband with high stopband rejections are achieved, and by increasing the number of resonant modes, improved frequency selectivity and better passband flatness are obtained. The analytical analysis well predicts the simulation and measurement results, which provides an efficient way for BPF designs. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:609-622, 2016.

In this paper, we present an area-efficient noise-optimized programmable 4 &times, 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic capacitor utilization in the DCOC loop and capacitive emitter degeneration in the variable-gain amplifier (VGA) stage, the chip area is minimized. Fabricated in a 0.13 &micro, m SiGe BiCMOS technology, the receiver achieved a small area of 0.54 mm2 per lane. The measured bit error rate (BER) is 10&minus, 12 with input signal varying from 110 &mu, App to 1150 &mu, App. The one-lane power dissipation values in the low-power and high-power modes are 84.97 mW and 123.75 mW, respectively.

In this paper, we explore the impact of changing the growth conditions on the substrate surface during the metal-organic vapor phase epitaxy of 2D-transition metal dichalcogenides. We particularly study the growth of molybdenum disulfide (MoS2) on sapphire substrates at different temperatures. We show that a high temperature leads to a perfect epitaxial alignment of the MoS2 layer with respect to the sapphire substrate underneath, whereas a low temperature growth induces a 30° epitaxial alignment. This behavior is found to be related to the different sapphire top surface re-arrangement under H2S environment at different growth temperatures. Structural analyses conducted on the different samples confirm an improved layer quality at high temperatures. MoS2 channel-based metal-oxide-semiconductor field-effect transistors are fabricated showing improved device performance with channel layers grown at high temperature.

Nowadays, more and more MMICs (Microwave Monolithic Integrated Circuit), such as limiters and switches, are designed to have balanced and unbalanced test pad structures to solve the challenging size restrictions and integration requirements for MMICs. Hybrid balanced and unbalanced RF (Radio Frequency) probes are adopted for an on-wafer test of the heteromorphy structures. The thru standard based on single balanced or unbalanced structures cannot meet the impedance matching requirements of the hybrid RF probes at the same time, which leads to a dramatic decreasing of the calibration accuracy and cannot satisfy the requirement of MMIC test. Therefore, in this paper, the calibration error estimating of hybrid RF probes based on traditional SOLR (Short Open Load Reciprocal) calibration method is performed, and an on-wafer test approach of MMIC based on hybrid balanced and unbalanced RF probes is proposed which combines the OSL (Open Short Load) second-order de-embedding technique with vector error correction and the matrix transformation technique. The calibration reference plane can be accurately shifted to the probe tip with this method, which greatly improves the test accuracy, and an automatic test system is built for this method based on the object-oriented C# language.

The design of the InP drain layer in asymmetric InGaAs/InP MOSFETs has been studied experimentally. The influence of doping and thickness of the InP drain has been carefully measured and compared with the performance with an InGaAs drain, regarding the output conductance, the voltage gain, and the leakage current. It is shown that the introduction of an undoped InP spacer has a profound effect on the transistor characteristics. Finally, the effect of a gate-connected field plate at the InP drain side has also been studied both in dc and RF data.

Regrown source/drain technology is highly appreciated in III-V MOSFET, to reduce the thermal budget induced by otherwise activation annealing required by ion implantation technology, as well as to reduce the source/drain resistances by highly doping the epitaxial materials. While regrown source/drain technology is facing the problems such as high parasitic source/drain capacitances and high electric field at the gate edge toward the drain side, leading to high drain leakage current. To relieve the leakage current problem as well as to improve the high frequency performances, low-k Si3N4 nitride spacer was introduced to the InGaAs MOSFET. Experimental results showed effective performance enhancements by applying nitride spacer in InGaAs MOSFET including drain leakage current and cutoff frequency.

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm2 (1.2 mm2 including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

InxGa1-xAsdevices have been widely researched for low power high frequency applications due to the outstanding electron mobility and small bandgap of the materials. Regrown source/drain technology is highly appreciated in InGaAs MOSFET, since it is able to reduce the thermal budget induced by ion implantation, as well as reduce the source/drain resistance. However, regrown source/drain technology has problems such as high parasitic capacitance and high electric field at gate edge towards the drain side, which will lead to large drain leakage current and compromise the frequency performance. To alleviate the drain leakage current problem for low power applications and to improve the high frequency performance, a novel Si3N4sidewall structure was introduced to the InGaAs MOSFET. Device simulation was carried out with different newly proposed sidewall designs. The results showed that both the drain leakage current and the source/drain parasitic capacitance were reduced by applying Si3N4sidewall together with InP extended layer in InGaAs MOSFET. The simulation results also suggested that the newly created “recessed” sidewall was able to bring about the most frequency favorable characteristic with no current sacrifice.

A new high-efficiency K-band MMIC medium-power amplifier (PA) is designed with multiharmonic matching using GaAs pHEMT process technology. It has an operation frequency centered at 26 GHz with a bandwidth of 2 GHz. A 20 dBm 1 dB-compression-point output power and 40% efficiency are achieved. A novel thermal reliability analysis method based on ICEPAK is proposed also to evaluate its thermal characteristic. The test result by using a QFI InfraScope™infrared imaging system is compared with the simulation result. It agrees well with an accuracy within ±1°C differences, which reflects the advantages of the thermal analysis method with respect to accuracy and convenience for use.

We have developed laterally asymmetric In0.53Ga0.47As/InP MOSFETs with different regrown contacts at the source (In0.53Ga0.47As) and the drain (InP). Introducing a wider bandgap material, InP, as the drain electrode, higher voltage gain gm/gd has been obtained with a reduced output conductance gd and improved breakdown voltage Vbd. For Lg = 50 nm, a high oscillation frequency fmax = 300 GHz has been obtained using an InP drain. A gate-connected field-plate has been introduced, which contributes to the device saturation with better impact ionization/band-to-band tunneling immunity.

In this paper, we present an all-in-one wafer-level solution for MMIC (monolithic microwave integrated circuit) automatic testing. The OSL (open short load) two tier de-embedding, the calibration verification model, the accurate PAE (power added efficiency) testing, and the optimized vector cold source NF (noise figure) measurement techniques are integrated in this solution to improve the measurement accuracy. A dual-core topology formed by an IPC (industrial personal computer) and a VNA (vector network analyzer), and an automatic test software based on a three-level driver architecture, are applied to enhance the test efficiency. The benefit from this solution is that all the data of a MMIC can be achieved in only one contact, which shows state-of-the-art accuracy and efficiency.

Asymmetric In0.53Ga0.47As MOSFETs with different regrown contacts at source (In0.53Ga0.47As) and drain (InP) have been developed. By introducing a wider bandgap material, InP as drain electrode, higher self-gain g(m)/g(d) has been obtained with reduced output conductance g(d) and improved break-down voltage V-bd. For L-g=100nm, a high oscillation frequency f(max)= 270GHz has been obtained using an InP drain.

The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al 2 O 3 /HfO 2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.

We present lattice matched (LM) In 0.53 Ga 0.47 As MOSHEMT and pseudomorphic (PM) In 0.75 Ga 0.25 As MOSHEMT with gate-first process as well as their related post process annealing (PPA) effects in this paper. PM In 0.75 Ga 0.25 As MOSHEMT with 7nm In 0.75 Ga 0.25 As inserted channel promotes higher DC and RF performances due to higher electron mobility with higher indium content of the channel. MOSHEMT structure is preferred to MOSFET structure since the channel layer is moved away from the oxide/semiconductor interface by using of an In 0.52 Al 0.48 As barrier layer between channel and Al 2 O 3 oxide. We obtain a high cut-off frequency ƒ T of 200GHz for a 100nm-gate-length device of PM In 0.75 Ga 0.25 As structure, which is 20GHz higher than the LM In 0.53 Ga 0.47 As MOSHEMT. The PPA process at 400°C for 1 minute in forming gas N 2 H 2 brings no difference to the DC and RF performances, showing that the detrimental effect of the interface defects is attenuated by using buried channel.

In this paper, a 200 nm n-channel inversion-type self-aligned In 0.53 Ga 0.47 As MOSFET with a Al 2 O 3 gate oxide deposited by Atomic Layer Deposition (ALD) is demonstrated. Two ion implantation processes using silicon nitride side-wall are performed for the fabrication of the n-type source and drain regions. The 200 nm gate-length MOSFET with a gate oxide thickness of 8 nm features the transconductance of 70 mS/mm and the maximum drain current of 200 mA/mm.

The performance of InGaAs metal oxide semiconductor field effect transistors with Al2O3 or HfO2 as gate oxide is evaluated and compared. The Al2O3 transistors show the lowest subthreshold slope and mid gap Dit, however, the HfO2 transistors reach a higher maximum transconductance (gmax) due to the higher oxide capacitance. Both high-κ dielectrics show a gm-frequency dispersion due to tunneling into border traps with a negligible activation energy as determined from temperature dependent measurements. The total amount of trapped charge at border traps is lower in the HfO2 devices. Scaling the HfO2 thickness further reduces the gm-frequency dispersion, possibly due to detrapping to the gate electrode.

Off-state drain leakage current has been investigated for InGaAs-based metal-oxide-semiconductor field-effect transistors with different drain configurations, InGaAs, and InP, respectively. The introduction of an InP drain presents a lower leakage current compared to InGaAs drain devices. From temperature dependent measurements, the leakage current mechanisms have been differentiated, and the role of drain direct band-to-band tunneling, as well as gate-induced drain leakage, has been identified.