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The nanoscale air channel device (NACD) has recently gained significant attention as a novel vacuum electronic that can be fabricated through nanofabrication technologies. Here, the research and progress of the NACD since it was reviewed, with a focus on working mechanism analysis, nanofabrication technologies, device structure optimization, electrode materials and simulation approach. Furthermore, the application fields and future development of NACD were summarized and prospected. The NACDs are expected to surpass the physical limits of traditional solid transistors due to its advantages such as smaller heat loss, high-speed, resistance to harsh environments.

Abstract In order to fulfill the complex cognitive behaviors in neuromorphic systems with reduced peripheral circuits, the reliable electronic synapses mimicked by single device that achieves diverse long‐term and short‐term plasticity are essential. Phase change random access memory (PCRAM) is of great potential for artificial synapses, which faces, however, difficulty to realize short‐term plasticity due to the long‐lasting resistance drift. This work reports the ruthenium‐doped Ge2Sb2Te5 (RuGST) based PCRAM, demonstrating a series of synaptic behaviors of short‐term potentiation, pair‐pulse facilitation, long‐term depression, and short‐term plasticity in the same single device. The optimized RuGST electronic synapse with the high transformation temperature of hexagonal phase >380°C, the outstanding endurance >108 cycles, the low resistance drift factor of 0.092, as well as the extremely high linearity with correlation coefficients of 0.999 and 0.976 in parts of potentiation and depression. Further investigations also go insight to mechanisms of Ru doping according to thorough microstructure characterization, revealing that Ru dopant is able to enter GST lattices thus changing and stabilizing atomic arrangement of GST. This leads to the short‐term plasticity realized by RuGST PCRAM. Eventually, the proposed RuGST electronic synapses performs a high accuracy of ~94.1% in a task of image recognition of CIFAR‐100 database using ResNet 101. This work promotes the development of PCRAM platforms for large‐scale neuromorphic systems.

Abstract Flexible electronics has emerged as a continuously growing field of study. Two‐dimensional (2D) materials often act as conductors and electrodes in electronic devices, holding significant promise in the design of high‐performance, flexible electronics. Numerous studies have focused on harnessing the potential of these materials for the development of such devices. However, to date, the incorporation of 2D materials in flexible electronics has rarely been summarized or reviewed. Consequently, there is an urgent need to develop comprehensive reviews for rapid updates on this evolving landscape. This review covers progress in complex material architectures based on 2D materials, including interfaces, heterostructures, and 2D/polymer composites. Additionally, it explores flexible and wearable energy storage and conversion, display and touch technologies, and biomedical applications, together with integrated design solutions. Although the pursuit of high‐performance and high‐sensitivity instruments remains a primary objective, the integrated design of flexible electronics with 2D materials also warrants consideration. By combining multiple functionalities into a singular device, augmented by machine learning and algorithms, we can potentially surpass the performance of existing wearable technologies. Finally, we briefly discuss the future trajectory of this burgeoning field. This review discusses the recent advancements in flexible sensors made from 2D materials and their applications in integrated architecture and device design.

Ultra-Low-Power Non-Volatile Memory (UltraRAM), as a promising storage device, has attracted wide research attention from the scientific community. Non-volatile data retention in combination with switching at ≤2.6 V is achieved through the use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. Along these lines, in this work, the structure, storage mechanism, and improvement strategies of UltraRAM were systematically investigated to enhance storage window clarity and speed performance. First, the basic structure and working principle of UltraRAM were introduced, and its comparative advantages over traditional memory devices were highlighted. Furthermore, through the validation of the band structure and storage mechanism, the superior performance of UltraRAM, including its low operating voltage and excellent non-volatility, was further demonstrated. To address the issue of the small storage window, an improvement strategy was proposed by reducing the thickness of the channel layer to increase the storage window. The feasibility of this strategy was validated by performing a series of simulation-based experiments. From our analysis, a significant 80% increase in the storage window after thinning the channel layer was demonstrated, providing an important foundation for enhancing the performance of UltraRAM. Additionally, the data storage capability of this strategy was examined under the application of short pulse widths, and a data storage operation with a 10 ns pulse width was successfully achieved. In conclusion, valuable insights into the application of UltraRAM in the field of non-volatile storage were provided. Our work paves the way for further optimizing the memory performance and expanding the functionalities of UltraRAM.

Hardware electronic synapse and neuro-inspired computing system based on phase change random access memory (PCRAM) have attracted an extensive investigation. However, due to the intrinsic asymmetric reversible phase transition, the defective weight update of PCRAM synapses in aspects of tuning range, linearity and continuity has long required a system-level complexity of circuits and algorithms. The cell-level improvements to a great extent may slim the system thus achieving efficient computing. We report in this work the great enhancement of Ge2Sb2Te5 (GST) based PCRAM synapses by combining materials engineering and pulse programming. It is found that carbon doping in GST retards the rate of phase changing thus increasing the controllability of the conductance, while non-linear programmable pulse excitations can eventually lead to a reliable synaptic potentiation and depression. A set of improved programmable pulse schemes for spike-timing dependent plasticity was then demonstrated, suggesting its potential superiority in flexible programming and reliable data collection. Our methods and results are of great significance for implementing PCRAM electronic synapses and high-performance neuro-inspired computing.

The results of the simulation the influence of the proton flux on the electrical characteristics of the device structure of dual-channel high electron mobility field effect transistor based on GaAs are presented. The dependences of the drain current ID and cut-off voltage on the fluence value and proton energy, as well as on the ambient temperature are shown.

A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET.

In the emerging process-based transistors, random telegraph noise (RTN) has become a critical reliability problem. However, the conventional method to analyze RTN properties may not be suitable for the advanced silicon-on-insulator (SOI)-based transistors, such as the fully depleted SOI (FDSOI)-based transistors. In this paper, the mechanism of RTN in a 22-nm FDSOI-based metal–oxide–semiconductor field-effect transistor (MOSFET) is discussed, and an improved approach to analyzing the relationship between the RTN time constants, the trap energy, and the trap depth of the device at cryogenic temperatures is proposed. The cryogenic measurements of RTN in a 22-nm FDSOI-based MOSFET were carried out and analyzed using the improved approach. In this approach, the quantum mechanical effects and diffuse scattering of electrons at the oxide–silicon interface are considered, and the slope of the trap potential determined by the gate voltage relation is assumed to decrease proportionally with temperature as a result of the electron distribution inside the top silicon, per the technology computer-aided design (TCAD) simulations. The fitted results of the improved approach have good consistency with the measured curves at cryogenic temperatures from 10 K to 100 K. The fitted trap depth was 0.13 nm, and the decrease in the fitted correction coefficient of the electron distribution proportionally with temperature is consistent with the aforementioned assumption.

Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

In the doped hafnia(HfO2)-based films, crystallization annealing is indispensable in forming ferroelectric phases. In this paper, we investigate the annealing effects of TiN/Hf0.5Zr0.5O2/TiN metal-ferroelectric-metal (MFM) capacitors by comparing microwave annealing (MWA) and rapid thermal annealing (RTA) at the same wafer temperature of 500 °C. The twofold remanent polarization (2Pr) of the MWA device is 63 µC/cm2, surpassing that of the RTA device (40 µC/cm2). Furthermore, the wake-up effect is substantially inhibited in the MWA device. The orthorhombic crystalline phase is observed in the annealed HZO films in the MWA and RTA devices, with a reduced TiN and HZO interdiffusion in MWA devices. Moreover, the MFM capacitors subjected to MWA treatment exhibit a lower leakage current, indicating a decreased defect density. This investigation shows the potential of MWA for application in ferroelectric technology due to the improvement in remanent polarization, wake-up effect, and leakage current.

This work investigates the responses of the fully-depleted silicon-on-insulator (FD-SOI) Hall sensors to the three main types of irradiation ionization effects, including the total ionizing dose (TID), transient dose rate (TDR), and single event transient (SET) effects. Via 3D technology computer aided design (TCAD) simulations with insulator fixed charge, radiation, heavy ion, and galvanomagnetic transport models, the performances of the transient current, Hall voltage, sensitivity, efficiency, and offset voltage have been evaluated. For the TID effect, the Hall voltage and sensitivity of the sensor increase after irradiation, while the efficiency and offset voltage decrease. As for TDR and SET effects, when the energy deposited on the sensor during a nuclear explosion or heavy ion injection is small, the transient Hall voltage of the off-state sensor first decreases and then returns to the initial value. However, if the energy deposition is large, the transient Hall voltage first decreases, then increases to a peak value and decreases to a fixed value. The physical mechanisms that produce different trends in the transient Hall voltage have been analyzed in detail.

This work investigates the behavior of fully depleted silicon-on-insulator (FD-SOI) Hall sensors with an emphasis on their physical parameters, namely the aspect ratio, doping concentration, and thicknesses. Via 3D-technology computer aided design (TCAD) simulations with a galvanomagnetic transport model, the performances of the Hall voltage, sensitivity, efficiency, offset voltage, and temperature characteristics are evaluated. The optimal structure of the sensor in the simulation has a sensitivity of 86.5 mV/T and an efficiency of 218.9 V/WT at the bias voltage of 5 V. In addition, the effects of bias, such as the gate voltage and substrate voltage, on performance are also simulated and analyzed. Optimal structure and bias design rules are proposed, as are some adjustable trade-offs that can be chosen by designers to meet their own Hall sensor requirements.