Search

Nonvolatile logic devices are crucial for the development of logic-in-memory (LiM) technology to build the next-generation non-von Neumann computing architecture. Ferroelectric field-effect transistors (Fe FET) are one of the most promising candidates for LiMs because of high compatibility with mainstream silicon-based complementary metal-oxide semiconductor processes, nonvolatile memory, and low power consumption. However, because of the unipolar characteristics of a Fe FET, a nonlinear XOR or XNOR logic gate function is difficult to realize with a single device. In addition, because single Fe polarization switch modulation is available in the devices, a reconfigurable logic gate usually needs multiple devices to construct and realize fewer logic functions. Here, we introduced polarization-switching (PS) and charge-trapping (CT) effects in a single Fe FET and fabricated a multi-field-effect transistor with bipolar-like characteristics based on advanced 10 nm node fin field-effect transistors (PS-CT FinFET) with 9 nm thick Hf

Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with a 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared with ferroelectric FinFET (Fe-FinFET) and ferroelectric lateral gate-all-around field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer vertical stacking, which further increases the integrated density of devices. Here, we develop ferroelectric vertical sandwich gate-all-around field-effect-transistors (Fe-VSAFETs) with large memory windows (the maximum 2.3 V), high program/erase speeds (100 ns), and excellent retention properties using a self-aligned high-k metal gate process. Furthermore, vertical nanosheet devices with two channel thicknesses of approximately 16 and 42 nm and nanowire devices with a channel diameter of 30 nm were successfully fabricated, and excellent device characteristics were obtained.

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/Hf x Zr1- x O2/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO2 or SiON) and Hf x Zr1- x O2 materials ( ${x} =0.75$ , 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization ( ${P}_{\text {s}}{)}$ of the Hf x Zr1- x O2 decreases from $25.9~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.5Zr0.5O2) to $20.3~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.6Zr0.4O2), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when ${P}_{\text {s}}$ further decreases to $8.1~ \boldsymbol {\mu }\text{C}$ /cm2 (Hf0.75Zr0.25O2), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of ${P}_{\text {s}}$ could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.

We theoretically investigated the effect of interface traps ( ${D}_{it}$ ) at the Si/SiO2 interface on the transient negative capacitance (NC) effect of the ferroelectric (FE) FETs. We used a metal/FE/interlayer/Si (MFIS) capacitor in series with a resistor to simulate the NC effect. Our simulation results show that appropriate ${D}_{it}$ can further improve the subthreshold swing (SS) by tuning the mismatch of the switching rate between free charges ( ${Q}_{f}$ ) and polarization charges ( ${P}$ ). In addition, we also analyzed the impact of different circuit parameters on the device performance. The following device design can improve the SS characteristics: thicker FE layer, thinner interlayer (DE), lower external resistance, and larger viscosity coefficient.

This article focuses on how to improve the negative capacitance (NC) properties of NMOSFET in the gate-last process flow. The impacts of the HfZrO ferroelectric film thickness, metal gates with different work functions, stress of filled metal gate, the thickness of seed layer underneath HfZrO etc. on NC effect are investigated, and the corresponding possible mechanisms are discussed. These techniques have been successfully applied to the fabrication of NC-NMOSFETs with physical thickness 1.5-nm HfZrO, and underneath with 1.0-nm ZrO2 seed layer. The NC-NMOSFETs with much improved subthreshold swing (SS) of 38.6 mV/decade and nearly hysteresis free are developed with a gate length of 900 nm, and the SS is over 40 mV/decade smaller than that of the control-2 NMOSFETs with 2.5-nm HfO2 gate dielectric only.

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high- ${k}$ metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed.

The trap characteristics and polarization effect on the trapping behavior in Hf0.5Zr0.5O2 ferroelectric field-effect transistors were analyzed. The current transient that corresponds to the trapping/detrapping of charge carriers was measured and the exact time constant spectra were extracted. In accordance with the different time constants and activation energies as well as the dependence of the trapping behavior on the filling conditions, traps that originated from the oxygen vacancies in the Hf0.5Zr0.5O2 layer and from the Si/SiO2 interface trap states were identified. The detrapping peaks in time constant spectra showed a consistent changing trend with the variation of remanent polarization, confirming that the positive polarization enhanced the trapping of charge carriers injected from channel side to the ferroelectric layer.

This article theoretically investigates the impact of charges at the ferroelectric/interlayer interface on the depolarization field of ferroelectric FET (FeFET) with metal/ferroelectric/interlayer/Si gate structure. The interfacial charges include fixed charges and trapped/detrapped charges. We find that the positive or negative interfacial charges (~1013 cm−2) can align the directions of the depolarization field and corresponding polarization in the ferroelectric. This article may provide insight into the device design of FeFET.

A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work.

The influence of the processing conditions on the interfacial and electrical properties of the high-k/SiGe gate stacks based on ozone oxidation is investigated. Detailed analyses of the relationship between the interface chemical structures and the corresponding electrical properties, as a function of oxidation time, reveal that the change in the distribution of the Ge atoms is the dominant factor to achieve superior electrical properties. In addition, the increase in the ratio of Si 4+ to Si 3+ of the oxide interlayer can help decrease the interface trap densities. These results provide us an important passivation route for the high-k/SiGe interface based on ozone oxidation, which is to explore an oxidation method that can realize an ultrathin interlayer including as much Si 4+ component as possible over a long oxidation time.

The HfO2-based Si ferroelectric field-effect transistor has been proposed as an emerging memory device due to its low write power, high speed, CMOS compatibility, and scalability. While the poor endurance limits its application, which is attributed to charge trapping and defect generation. In this work, we investigate the effect of the minor loop operation on defect generation. We find that using a minor loop operation, the trap generation is suppressed, which is quantitively extracted by the low-frequency noise method. We get the endurance of 6 × 107 cycles for Si FeFET with a Hf0.5Zr0.5O2 ferroelectric layer through minor hysteresis loop operation.

We examined the wake-up effect in a TiN/Hf0.4Zr0.6O2/TiN structure. The increased polarization was affected by the cumulative duration of a switched electric field and the single application time of the field during each switching cycle. The space-charge-limited current was stable, indicating that the trap density did not change during the wake-up. The effective charge density in the space-charge region was extracted from capacitance–voltage curves, which demonstrated an increase in free charges at the interface. Based on changing characteristics in these properties, the wake-up effect can be attributed to the redistribution of oxygen vacancies under the electric field.

Since defects such as traps and oxygen vacancies exist in dielectrics, it is difficult to fabricate a high-performance MoS2 field-effect transistor (FET) using atomic layer deposition (ALD) Al2O3 as the gate dielectric layer. In this paper, NH3 in situ doping, a process treatment approach during ALD growth of Al2O3, is used to decrease these defects for better device characteristics. MoS2 FET has been well fabricated with this technique and the effect of different NH3 in situ doping sequences in the growth cycle has been investigated in detail. Compared with counterparts, those devices with NH3 in situ doping demonstrate obvious performance enhancements: I on/I off is improved by one order of magnitude, from 1.33 × 105 to 3.56 × 106, the threshold voltage shifts from –0.74 V to –0.12 V and a small subthreshold swing of 105 mV/dec is achieved. The improved MoS2 FET performance is attributed to nitrogen doping by the introduction of NH3 during the Al2O3 ALD growth process, which leads to a reduction in the surface roughness of the dielectric layer and the repair of oxygen vacancies in the Al2O3 layer. Furthermore, the MoS2 FET processed by in situ NH3 doping after the Al and O precursor filling cycles demonstrates the best performance; this may be because the final NH3 doping after film growth restores more oxygen vacancies to screen more charge scattering in the MoS2 channel. The reported method provides a promising way to reduce charge scattering in carrier transport for high-performance MoS2 devices.

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window decreases: 1) The ferroelectric characteristic of Hf0.5Zr0.5O2 is not degraded. 2) The trap density in the upper bandgap of the gate stacks increases. 3) The reason for memory window decrease is increased trapped electrons after program operation but not related to hole trapping/de-trapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process., 6 pages,9 figures

HfO2-based ferroelectric materials have been widely studied for their application in ferroelectric FETs, which are compatible with conventional CMOS processes, however, problems with the material’s inherent fatigue properties have limited its potential for device application. This paper systematically investigates the effects of tensile stress and annealing temperature on the endurance and ferroelectric properties faced by Zr-doped HfO2 ferroelectric film. The remnant polarization (Pr) shows an increasing trend with annealing temperature, while the change in the coercive electric field (Ec) is not obvious in terms of the relationship with tensile stress or annealing temperature. In addition, the application of tensile stress does help to improve the endurance characteristics by about two orders of magnitude for the ferroelectric material, and the endurance properties show a tendency to be negatively correlated with annealing temperature. Overall, although the effect of stress on the ferroelectricity of a HZO material is not obvious, it has a great influence on its endurance properties and can optimize the endurance of the material, and ferroelectricity exhibits a higher dependence on temperature. The optimization of the endurance properties of HZO materials by stress can facilitate their development and application in future integrated circuit technology.

The applicability of the Gibbs free energy landscape to the definition and understanding of negative capacitance in a ferroelectric capacitor is investigated. We find that the Gibbs free energy cannot define the transient negative capacitance. In order to define the negative capacitance, we suggest returning to the original definition of capacitance, which is the second-order derivative of electrostatic force work with respect to polarization.

Based on the transient NC theory, the impact of interfacial traps at SiO 2 /Si interface $(D_{it})$ is studied in this work. We use the NCFET that with Metal/Ferroelectric/Interlayer/Semiconductor (MFIS) gate structure in our simulation. Our work points out that the $D_{it}$ can reduce the subthreshold swing (SS) by improving the transient NC effect. The physical origin is the tuning of the mismatch between the free charges $(Q_{f})$ and polarization $(P)$ by $D_{it}$ . Our work shows that the $D_{it}$ can tune the transient NC phenomenon.

The impact of various postdeposition annealing (PDA) ambiences (N2, O2, and NH3) on the hole mobility of germanium (Ge) pMOSFET with GeO2/Al2O3 gate-stack is investigated. It is found that the mobility is about 10% higher after N2 PDA, while it is about 10% smaller after O2 and NH3 PDA than that without PDA. The physical origin is attributed to the remote Coulomb scattering. The Ge/GeO2 interface charge Q1 decreases, but the GeO2/Al2O3 interface dipole Qdipole increases after PDA in N2, O2, and NH3. The higher mobility after N2 PDA is due to a smaller Q1 and Qdipole, while the lower mobility after O2 and NH3 PDA is due to a larger Qdipole. All these three PDA ambiences are beneficial to reduce the gate leakage current. Therefore, PDA in N2 is a balance approach for both the hole mobility improvement and gate leakage current reduction.

High-performance negative capacitance p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high- ${\kappa }$ metal gate FinFETs fabrication flow. The devices show improved subthreshold swing values [34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices] and slight hysteresis voltages (~9 mV for $\textsf {L}_{\textsf {G}} = \textsf {500}$ nm and ~40 mV for $\textsf {L}_{\textsf {G}} = \textsf {20}$ -nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low-interface state density ( ${D}_{\sf it}$ ) and the perfect channel electrostatic integrity.

This work investigates the impact of mobility degradation on endurance fatigue of a ferroelectric field-effect-transistor (FeFET) with the TiN/Hf0.5Zr0.5O2/SiOx/Si (MFIS) gate structure. We use the split capacitance–voltage ( C– V) method to study the carrier mobility during the program/erase cycling. We find that significant mobility degradation occurs with increasing program/erase cycle and further deteriorates endurance characteristics. Our work provides mobility degradation as another endurance fatigue factor of FeFET besides charge trapping and trap generation, which is helpful for endurance improvement.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

This paper investigates the thermodynamic driving force of transient negative capacitance (NC) in the series circuit of the resistor and ferroelectric capacitor (R-FEC). We find that the widely used Landau-Khalatnikov (L-K) theory, that is, the minimum of the Gibbs free energy, is inapplicable to explain the transient NC. The thermodynamic driving force of the transient NC phenomenon is the minimum of the difference between the elastic Gibbs free energy and the electric polarization work. The appearance of the transient NC phenomenon is not due to the widely accepted view that the ferroelectric polarization goes through the negative curvature region of elastic Gibbs free energy landscape (Ga). Instead, the transient NC phenomenon appears when the energy barrier of Ga disappears. The transient NC is dependent on both the intrinsic ferroelectric material parameters and extrinsic factors in the R-FEC circuit., 31 pages, 7 fiures, 1 table