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Emotional intelligence plays an important role in artificial intelligence. The brain circuitry of emotion mainly includes the prefrontal cortex, the amygdala, hippocampus and et al. Many brain emotional learning models were proposed in recent years, the existing brain emotional learning models failed to consider the contextual information in practical applications, and do not discuss the corresponding circuit implementation. In this paper, a context-dependent emotional learning network and its memristive circuit implementation are introduced. The added context-dependent module is used to process the contextual information, which makes the network context-dependent when receiving the same input signals. For circuit implementation, the memristive circuit design mainly contains the amygdala module and orbitofrontal cortex module, which imitates the emotion learning process in the brain. Besides, a multi-input multi-output memristive circuit of the context-dependent emotional network is applied to multi-task classification. PSPICE simulation results verified the adaptability and flexibility of the context-dependent emotional learning network.

Aiming at the problem that position errors accumulate rapidly in foot-mounted pedestrian navigation systems using a low-cost inertial sensor, a novel three-dimensional (3D) positioning method is proposed. First, when the foot is still, an improved zero velocity detection method that assigns different weights to each inertial measurement unit (IMU) data in a sliding window is designed to reduce positioning errors. When the foot is in swing, a lateral velocity restriction method is proposed by analyzing the gait characteristics of pedestrians. In addition, when pedestrians need altitude positioning in the building, the stair step height is also applied to the zero-velocity update (ZUPT)-aided inertial navigation system, which can effectively improve altitude positioning accuracy. Experiments under multi-gait modes show that the proposed zero velocity detection method can achieve smaller positioning errors compared with other traditional zero velocity detection methods. Moreover, the trajectory estimated by the proposed method has a higher coincidence with the real trajectories, the two-dimensional (2D) plane positioning error is less than 0.9% and the average altitude positioning error is only 0.12 m.

To enhance the performance of the inertial navigation system (INS)/global position system (GPS) integrated navigation system for the land vehicle during GPS outages is an extremely challenging task. Though existing researches have made reasonable progress in positioning accuracy, they largely ignore sophisticated vehicle stopping events, and the further improvement of positioning performance is urgently needed in complex urban environments. In this article, we propose a heterogeneous multi-task learning (MTL) structure with a shared de-noising process to conduct pseudo-GPS position prediction and zero-velocity detection. The raised model builds upon three vital parts: 1) a shared de-noising convolutional autoencoder (CAE), which can effectively filter the measurement noises in the original inputs and provide more clean data for subsequent calculations without the ground-truth sensor data; 2) a predictor that uses a deep temporal convolutional network (TCN) to predict pseudo-GPS position to bridge GPS gaps; and 3) a robust zero-velocity detector that utilizes a 1-D deep convolutional neural network to accurately detect the vehicle stationary pattern, allowing for timely correcting the velocity and heading. Our proposed MTL model is evaluated on extensive practical road data and achieves a root mean square error of 3.794 m for 120-s GPS outages under long-term vehicle stopping scenarios, which obviously outperforms the stand-alone long short-term memory, TCN, and TCN + CAE. Experimental results also demonstrate that our proposed MTL method yields a remarkable accuracy of over 99.0% for vehicle stationary detection.

Positioning accuracy and power consumption are essential performance indicators of integrated navigation and positioning chips. This paper proposes a single-frequency GNSS/MEMS-IMU/odometer real-time high-precision integrated navigation algorithm with dynamic power adaptive adjustment capability in complex environments. It is implemented in a multi-sensor fusion navigation SiP (system in package) chip. The simplified INS algorithm and the simplified Kalman filter algorithm are adopted to reduce the computation load, and the strategy of adaptively adjusting the data rate and selecting the observation information for measurement update in different scenes and motion modes is combined to realize high-precision positioning and low power consumption in complex scenes. The performance of the algorithm is verified by real-time vehicle experiments in a variety of complex urban environments. The results show that the RMS statistical value of the overall positioning error in the entire road section is 0.312 m, and the overall average power consumption is 141 mW, which meets the requirements of real-time integrated navigation for high-precision positioning and low power consumption. It supports single-frequency GNSS/MEMS-IMU/odometer integrated navigation SiP chip in real-time, high-precision, low-power, and small-volume applications.

Aiming at the GNSS receiver vulnerability in challenging urban environments and low power consumption of integrated navigation systems, an improved robust adaptive Kalman filter (IRAKF) algorithm with real-time performance and low computation complexity for single-frequency GNSS/MEMS-IMU/odometer integrated navigation module is proposed. The algorithm obtains the scale factor by the prediction residual, and uses it to adjust the artificially set covariance matrix of the observation vector under different GNSS solution states, so that the covariance matrix of the observation vector changes continuously with the complex scene. Then, the adaptive factor is calculated by the Mahalanobis distance to inflate the state prediction covariance matrix. In addition, the one-step prediction Kalman filter is introduced to reduce the computational complexity of the algorithm. The performance of the algorithm is verified by vehicle experiments in the challenging urban environments. Experiments show that the algorithm can effectively weaken the effects of abnormal model deviations and outliers in the measurements and improve the positioning accuracy of real-time integrated navigation. It can meet the requirements of low power consumption real-time vehicle navigation applications in the complex urban environment.

A fully integrated single input, dual-channel, single-band reconfigurable GNSS radio frequency receiver supporting GPS, BD2 and Galileo systems is designed and implemented in a 0.18 ​μm CMOS process for portable Internet of Things applications. The receiver incorporates a single RF front-end, low-power fractional-N synthesizer, and reconfigurable complex band-pass filter, which can be flexibly configured to receive GPS L1/BD2 B1 or GPS L1/Galileo E1, and any of these signals separately, and can also effectively simplify the design complexity of the receiver and reduce power consumption. Moreover, a flexible frequency plan is employed to meet the different frequency requirements of the receiver. While drawing 16 ​mA current from a 1.8 ​V supply, this RF receiver achieves a total noise figure of 1.79 ​dB, a maximum voltage gain of 108 ​dB, a gain dynamic range of 56 ​dB and the input third-order intercept point of - 18 . 09 dBm and - 23 . 66 dBm at 1575 ​MHz and 1561 ​MHz, respectively, with an active die area of 1.86 ​mm2.

In this paper, a modified closed-loop auto frequency calibration technique (MCL-AFC) is adopted in an integer-N phase-locked loop (PLL) for GPS-L1 application. The ignorance of circuit initial cond...

Kalman filter is a commonly used method in the Global Navigation Satellite System (GNSS)/Inertial Navigation System (INS) integrated navigation system, in which the process noise covariance matrix has a significant influence on the positioning accuracy and sometimes even causes the filter to diverge when using the process noise covariance matrix with large errors. Though many studies have been done on process noise covariance estimation, the ability of the existing methods to adapt to dynamic and complex environments is still weak. To obtain accurate and robust localization results under various complex and dynamic environments, we propose an adaptive Kalman filter navigation algorithm (which is simply called RL-AKF), which can adaptively estimate the process noise covariance matrix using a reinforcement learning approach. By taking the integrated navigation system as the environment, and the opposite of the current positioning error as the reward, the adaptive Kalman filter navigation algorithm uses the deep deterministic policy gradient to obtain the most optimal process noise covariance matrix estimation from the continuous action space. Extensive experimental results show that our proposed algorithm can accurately estimate the process noise covariance matrix, which is robust under different data collection times, different GNSS outage time periods, and using different integration navigation fusion schemes. The RL-AKF achieves an average positioning error of 0.6517 m within 10 s GNSS outage for GNSS/INS integrated navigation system and 14.9426 m and 15.3380 m within 300 s GNSS outage for the GNSS/INS/Odometer (ODO) and the GNSS/INS/Non-Holonomic Constraint (NHC) integrated navigation systems, respectively.

Aiming to improve the navigation accuracy during global navigation satellite system (GNSS) outages, an algorithm based on long short-term memory (LSTM) is proposed for aiding inertial navigation system (INS). The LSTM algorithm is investigated to generate the pseudo GNSS position increment substituting the GNSS signal. Almost all existing INS aiding algorithms, like the multilayer perceptron neural network (MLP), are based on modeling INS errors and INS outputs ignoring the dependence of the past vehicle dynamic information resulting in poor navigation accuracy. Whereas LSTM is a kind of dynamic neural network constructing a relationship among the present and past information. Therefore, the LSTM algorithm is adopted to attain a more stable and reliable navigation solution during a period of GNSS outages. A set of actual vehicle data was used to verify the navigation accuracy of the proposed algorithm. During 180 s GNSS outages, the test results represent that the LSTM algorithm can enhance the navigation accuracy 95% compared with pure INS algorithm, and 50% of the MLP algorithm.

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180nm CMOS Mixed-Signal process while it operates under 1.8V supply voltage. The measured output frequency of PLL is 1.571GHz and output power is -1.418dBm. The in-band phase noise is -98.1 dBc/Hz @ 100kHz, while the out-band phase noise is -130.3dBc/Hz @ 1MHz. The reference spur is -75.8dBc at 16.368MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2µs.

This paper presents a less-occupied and ultra-low noise LDO structure. This structure can achieve ultra-low noise performance without large filter capacitor by incorporating a capacitance amplifying circuit in the structure of LDO with pre-regulation. A large amount of chip area will be saved in this structure. A novel LDO in proposed structure is realized under SMIC 0.18 μm process. The experiment results show that proposed LDO structure can achieve a total output noise of 25.5 μV between 10 Hz and 1 kHz and 56.4 μV between 1 kHz and 1 MHz with a filter capacitor of 5pF. PSR is ?71.6 dB under low frequency until 49 kHz and at least ?65.7 dB under entire frequency range.

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm2. Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.

A general synthesis method for the realisation of nth-order current transfer function is derived from signal-flow graph. From the proposed method, a novel configuration of nth-order current-mode universal filter using differential voltage current conveyors (DVCCs) and multiple outputs DVCC (MODVCC) is obtained. The number of active elements in the configuration is reduced to n + 1, which is a significant reduction in comparison with the previously reported methods. The proposed circuits employ the features of multifunctional, smallest number elements, simple in structure, easy to be cascaded and convenient for integration. As examples, a biquadratic filter and other four different orders filters are realised in 0.18 µm CMOS process. Simulation results are given to demonstrate the effectiveness of the schemes. The simulation results are found to be in good agreement with the theory.

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7 pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200 × 280 µm2. The simulation results under mixed-signal 0.18 µm 1P6M process show that this novel LDO's output voltage can recover within 1.7 µs (rising) and 2.41 µs (falling...

A state variable block diagram method is given for the realization of universal biquadratic transfer functions employing second-generation current-controlled conveyors (CCCIIs). Using minimum number of passive components and properly adjusting the bias currents of CCCIIs, the proposed circuits can realize all the tunable frequency standard filter functions: high-pass, band-pass, low-pass, notch-pass, and all-pass by choosing appropriate input branches without changing the passive elements. These presented circuits are in current-mode and voltage-mode separately. The non-ideality analyses of these configurations are given. Additionally, a high-order low-pass filter derived from the proposed voltage-mode biquadratic filter is introduced. PSPICE simulation results are included to verify the theory.

Two new universal active current-mode filters are proposed, one topology of which is with three inputs and one output, the other prototype is with single input and three outputs counterpart. One proposed circuit employs two current conveyors, two grounded capacitors and two resistors, wherever the other proposed circuit employs two current conveyors, two grounded capacitors and two multi-input, multi-output Operational Transconductance Amplifiers(OTA) as variable resistor for tuning the cutoff frequency of realized filters. Without changing the passive elements, the proposed circuits employ features of multifunctional, convenient for integration, low sensitivities and simple in structure.

This paper discusses a circuit of 12-b, 150 MHz Sample/s current steering DAC with hierarchical symmetrical switching sequences which will compensate gradient error. The circuit of 12-b DAC employs segmented architecture, the least significant bits (LSB's) steer a binary weighted array, while the most significant bits (MSB's) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ± 0.6 least significant bit (LSB) and ±0.9 LSB, respectively. The output spectrum of the DAC is ?63 dB with an input frequency of 30 MHz at 150 MHz conversion rate. The circuit is fabricated in 0.5 ? ?m, two-poly two-metal, 5.0 V, mixed-signal CMOS process and occupies 1.27 × 0.96 mm, when operating at 150 MHz Sample/s, it dissipates 91.6 mW from 5.0 V power supply which is much lower than those of [1].

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138 kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3 V power supply and 0.35 μm CMOS technology. Chip test results demonstrate better than −68 dB THD with 70 kHz, 2.0 V pp signal, frequency turning range of more than 14,000 from 3 Hz to 420 kHz, chip area of 0.36 mm 2 and power consumption of 16 mW.

A fully differential R-MOSFET-C fourth-order Bessel active low-pass filter employing passive resistors and current-steering MOS transistors as a variable resistor is proposed. The implementation relies on the tunability of the current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the group delay of the Bessel active filter can be realized accurately. A 0.75 us group delay 520 kHz frequency fourth-order Bessel lowpass filter based on a passive doubly terminated RLC prototype was designed and fabricated using 3.3 V power supply and 0.35 um CMOS technology. Chip test results demonstrate better than −65 dB THD with @100 kHz, 1.65-Vpp signal, frequency tuning range of more than ten decades from 0.6 kHz to 550 kHz, chip area of 0.32 mm2 and power consumption of 13.3 mW.

This paper proposed a novel tunable current-mode square-wave converter with current-rectifying function. The converter has a concise and simple structure without using any passive devices, and all the active devices of the converter are grounded, which makes it convenient for IC application. The proposed converter can generate both positive and negative square-wave signals whose amplitude can be adjusted independently by the bias ports. Also it can produce positive half-wave, negative half-wave, positive full-wave, and negative full-wave rectifying current outputs. The PSPICE simulation results of the converter based on 0.25µm CMOS process are presented. The results show that the analysis method is valid and effective

This paper proposed a novel second-order versatile filter employing Current Controlled Current Differencing Current Conveyor (CCCDCC) and Multi-Output Operational Transconductance Amplifier (MO-OTA). The proposed filter has a SISO (Single Input Single Output) structure which can serve as low-pass, high-pass, band-pass band-stop and all-pass filter by changing the bias signals. Moreover, both of the frequency and amplitude of the filter can be adjusted electronically. The PSPICE simulation results of the proposed filter based on 0.25µm CMOS process are presented; the results show that the analysis method is valid and effective.

In this paper, a new equivalent circuit-level model of QCLs is introduced to overcome drawbacks of the previous models. The photon gain coefficient and injection current efficiency both depend on the injector doping density in the model. A revised three-level rate equations that permit a compact and computationally efficient implementation. The electron scattering time, relaxation time and escape time between the corresponding levels are obtained by employing a fully non-equilibrium self-consistent Schrodinger-Poisson analysis of the scattering rate and energy balance equations. A general diode sub-circuit is adopted to model the current-voltage relationship. This new circuit-level model can be readily incorporated into a standard circuit simulation environment such as SPICE, which enables electronic integrated circuit designers to simultaneously evaluate the performance of both QCL and electronic devices.

An equivalent circuit thermal model is established based on quantum cascade laser(QCL) two-level rate equation by analyzing the gain characteristic depend on the temperature in active region. The model enables the analysis of the thermal characteristics of intermediate infrared QCL using general circuit analysis software such as PSPICE. The simulation results are in agreement with reported theoretical and experimental data. That proves the practicality and accuracy of the model.