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In this work, body diode stress has been carried out for 1700 V 25 mΩ planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of 250-400 A (about 1000-1600 A/cm2) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased RDSon was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.

This work details two approaches with multi-epitaxial growth to create a vertical superjunction structure made of alternating pillars. One approach is a chain of very high energy implants, the other uses a preferred implantation direction to achieve a channeled profile. The manufactured devices show a breakdown voltage of 1000 V for channeled, two-step epi with total 4.9 μm thickness. 800 V for regular high energy implants using three epi steps of total 3.7 μm thickness. The measured Rsp was 0.7 mOhm*cm2 for dies with size 0.018 cm2. UIS and temperature measurement show reliable performance. The channeled implant looks favorable to reduce the number of process steps needed to create an efficient superjunction structure.

Similar charge to failure distributions with mean values of about 50 C/cm2 were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with IG=1 mA/cm2 at T=150 °C. No substantial difference in VTH drift rate with VGS=28 V at T=150 °C was found after about 10 s recovery period for IG stressed devices compared with unstressed devices. Additionally, IG stressed and unstressed devices did not differ in final VTH shift at T=25 °C after VGS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm2 pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in VTH and RDSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

In this work, threshold voltage drift of SiC MOSFET devices have been investigated. The drift during positive gate bias application was found to be moderate for three commercial grade devices, while the results for negative gate bias application differ widely. We demonstrate ON Semiconductor SiC MOSFETs with threshold voltage stability under both positive and negative bias stress due to an improved gate oxide process, and the influence of high field stress on the threshold voltage is additionally discussed. A long term transient high temperature gate bias stress is shown to cause a slight positive shift in the threshold voltage of the ON Semiconductor devices, while the on resistance remains constant.

This paper proposes a charge-to-breakdown (Q BD ) approach for SiC/SiO 2 dielectric lifetime extraction. The current through the dielectric is shown to be a combination of Fowler Nordheim (FN) and thermally assisted tunneling (TAT). The former leads to positive charge trapping, the latter to negative charge storage in border traps near the SiC/SiO 2 interface. Both degradation mechanisms have a distinctly different failure distribution function. Time-to-fail extracted from constant field TDDB (standard industry technique) is unable to capture the effects of these different charge trapping mechanisms on the failure distribution function, in contrast to constant current Q BD stress. Hence, time-to-fail from Q BD stress leads to a more accurate and physics based lifetime prediction.

In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

1200 V 80 m Ω SiC MOSFETs were developed for 150 mm wafer mass production. Avalanche ruggedness was confirmed by measuring the failure distribution in unclamped Inductive switching (UIS) for five wafers. The high voltage blocking reliability was verified by running 1000hr high temperature reverse bias tests for totally 770 devices without failures. The process conditions were optimized for gate oxide integrity and to minimize threshold voltage (V TH ) drift both during positive and negative bias stress. Significant reductions of extrinsic defects in the gate oxide breakdown distributions were obtained using optimized process conditions for both product dies and NMOS capacitors. State-of-the-art V TH stability was verified by transient measurements of V TH drift during gate bias stress for packaged 80 m ΩSiC MOSFETs.