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Lock-in thermography (LIT) phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. This paper describes how the use of new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, can result in improvements to data repeatability and accuracy as well as faster time to results. The new software is applied to generate the empirical phase shift versus applied lock-in frequency plot using 2.5D IC devices with known defect location. Subsequently, experimental phase shift data from reject 2.5D IC devices with unknown defect locations are obtained and compared against the empirical phase shift plot. The defect Z-depth of these devices are determined by comparing where the experimental phase shift data points lies with respect to empirical phase shift plot and validated with physical failure analysis (PFA).

This paper describes a 2X improvement in phase data acquisition for Lock-in Thermography (LIT). Phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. To overcome these difficulties, new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, are employed to validate improvements to data repeatability and accuracy as well as faster time to results on different advanced packaging devices such as flip chips and stack dies. Overall, our results showed a 2X faster time to more accurate and repeatable data for X, Y, and Z depth localization.

Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

In this paper we evaluate the possibility of extending Time Resolved Emission (TRE) technology towards future low voltage SOI technologies. In particular, we investigate and quantify the gain offered by the InGaAs detector improvements devised by Credence Corp., now DCG Systems, the manufacturer of the Emiscope III PICA system used in this analysis. Experiments on a test chip fabricated in the IBM SOI 65 nm technology will demonstrate that the improved tool guarantees the same Signal-to-Noise Ratio (SNR) even at ~90 mV lower supply voltages. In the second part of the paper we also discuss various other acquisition optimizations of the system. Although the analysis presented here refers to a specific tool, the large majority of the results and discussions can easily be generalized and applied to other PICA systems and detectors, as well as low voltage bulk silicon technologies.

Ultra low voltage probing by time resolved emission (TRE) technology below 1.0V is very challenging for micro-processor debug in practical operation condition. This is because the photo-emission rate reduces exponentially as the power supply voltage decreases. In this paper, a novel technology with improved detector in solid immersion lens (SIL) TRE system was demonstrated for low voltage and small node probing. An improved detecting scheme was developed to collect 30% more photon detection efficiency than the previous system. The SIL TRE with low dark noise detector technology has been successfully applied to optical probing for 45nm product debug. The performance gain improvement in strong and weak signal regime has been demonstrated against the current detector technology. It has also demonstrated the capability on probing the ultra low voltage at 0.75 V for sub micron node of 45nm process.

Time-resolved photon emission has been shown to be useful in analyzing clock skews and timing-related defects in flip-chip devices. In practice, time-resolved photon emission using the S-25 Quantar detector cannot be used at long loop lengths (typically >10 μs). This paper discusses a near-infrared (NIR) optimized time-resolved emission system to demonstrate that even with long loop lengths time-resolved photon emission can be extremely useful for defect localization. Specifically, it describes time-resolved photon emission system, and shows how time-resolved photon emission was used to solve two different issues that caused scan fails on silicon-on-insulator devices, and briefly discusses the interpretation of optical waveforms. The two issues are presented as case studies.

Dynamic hot-electron emission using time-resolved photon counting can address the long-term failure analysis and debug requirements of the semiconductor industry's advanced devices. This article identifies the detector performance parameters and components that are required to scale and keep pace with the industry's requirements. It addresses the scalability of dynamic emission with the semiconductor advanced device roadmap. It is important to understand the limitations to determining that a switching event has occurred. The article explains the criteria for event detection, which is suitable for tracking signal propagation and looking for logic or other faults in which timing is not critical. It discusses conditions for event timing, whose goal is to determine accurately when a switching event has occurred, usually for speed path analysis. One of the uses of a dynamic emission system is to identify faults by studying the emission as a general function of time.