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To characterize the power consumption of a macrocell, a general method involves recording the power consumption of all possible input transition events in the look-up tables. However, though this approach is accurate, the size of the table becomes very large. In this paper, we propose a new power modeling technique that takes advantage of the structural information of a macrocell. In this approach, a subset of primary inputs and internal nodes in the macrocell are selected as the state variables to build a state transition graph (STG). These state variables can model the steady-state transitions completely. Moreover, by selecting the characterization patterns properly, the STG can also model the glitch power in the macrocell accurately. To further simplify the complexity of the STG, an incomplete power modeling technique is presented. Without losing much accuracy, the property of compatible patterns is exploited for a macrocell to further reduce the number of edges in the corresponding STG. Experimental results show that our modeling techniques can provide SPICE-like accuracy, while the size of the look-up table is significantly reduced.

Reducing the power supply voltage is an effective technique to reduce dynamic power. Power shut-off (PSO) is also a well-known approach to reduce leakage power. In practice, one may employ multi-supply voltage or dynamic voltage and frequency scaling (DVFS) techniques accompanied with power gating and multi-depth sleep modes to reduce both of dynamic and leakage power consumption. As the voltage domains (power domains) and sleep modes (power modes) are increased dramatically, it is difficult to plan interface logics such as level shifters and isolation cells completely by manual for each power domain. In this paper, we present an interface planning methodology, and take a DVFS and power gating design with over 50 power domains and 80 power modes to demonstrate the verification challenges and our solutions. Besides, we propose a “seamless” interface control circuit for PSO and DVFS designs. By using the circuit, the designs in the power on domain don't feel any data change when the opposite power domain is powered off.

We present our experience of DFM (design for manufacturability) and DFY (design for yield) considerations on physical designs at 0.13 mum and below technology nodes. The impact of some DFM approaches on timing and signal integrity are addressed. We also present our experience of yield analysis and improvement for the designs with process variation and dynamic IR drop issues.

This paper presents a novel methodology for the average power estimation. According to the power information obtained from logic-level simulation, we first perform pattern compaction and derive the relative weighting factors, and then perform accurate transistor-level power simulation by using the compact sequence. Combining both the weighting factors and the accurate power dissipation data, we calculate and report the estimated average power dissipation. Finally, we verify our method by using some practical industrial design examples with their functional simulation patterns. The experimental results show that our approach could speed up to two orders of magnitude without losing too much accuracy.