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With the deployment of wide-area measurement systems (WAMS) equipment, dynamic security assessment (DSA) based on artificial intelligence (AI) has more and more advantages. For the power system, the number of transient stable cases is much larger than that of unstable cases, which leads to insufficient learning of unstable cases and affects the evaluation effect of the model. In addition, during the stability assessment process of the power system, the misjudgment cost of unstable case is much higher than that of stable case. Based on the above two points, we proposed a DSA method of power system based on improved XGBoost. The proposed method introduces the weight adjustment factor into the loss function to balance the quantity variance of two type cases and the difference of misjudgment cost, which greatly reduces the misjudgment rate of unstable samples. The test results on IEEE 16-machine 68-bus test system and IEEE 50-machine 145-bus test system show that the proposed method can have higher recognition of the unstable samples and can be applied to DSA.

This work focuses on resolving high ESR issue in standard MIM templates. The solutions have been deployed to tens-of-Gbps high-speed serial links to minimize power noise and supply-induced jitter. New aspects of this work are: (1) MIM templates and their associated power/ground grid are optimized to minimize ESR and achieve good area utilization. These modular designs allow simplicity and flexibility in implementation. (2) Accurate ESR calculation methodology for simple MIM structures is developed. It correlates well with layout extraction using commercial tools.

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.

The methods of estimating recovery factor of newly added measured reserves in existing petroleum reserves standardization of China are unsuitable for sandstone oil reservoirs of extra-low permeability with water flooding, so new empirical formula method and analogous method for estimating recovery factor of the reservoirs are studied. The key parameters influencing recovery factor are permeability, formation oil viscosity, porosity, mobility and well spacing density. Based on the requirements such as longer development time, reliable reserves and available reservoir parameters, 37 sandstone oil reservoirs of extra-low permeability were selected, and 19 recovery factor models were summarized. With consideration of high multiple regression coefficient and low standard error, 4 empirical formulae suitable for reservoir of water-flood development with vertical well were established. Comparison of calculated results from the empirical formulae and calibrated recovery factors of PetroChina recently shows that the formulae match well. It is important to choose reservoir with successful pilots and/or developed in large scale as benchmark reservoirs in the analogy estimation. Based on the principle of keeping consistent of analogous method with production performance, a practical example of Chang 8 reservoir, Triassic, FX oilfield was given to illustrate the determination of recovery factor of extra-low permeability reservoir. Empirical formula method and analogous method have their advantages and disadvantages, reserves estimators should pay great attention to the reliability of data, to application condition for empirical formula method and to the avoidance of single reservoirs in analogous method. Key words: extra-low permeability, sandstone reservoir, waterflood development, recovery factor calibration, empirical formula method, analogous method, measured reserves, proved reserves

Background As a highly conserved system, the activation of the Notch pathway has been implicated in the tumorigenesis of various hematologic diseases, including leukemias, lymphomas, and multiple myeloma. The Notch3 receptor is frequently expressed in T-cell acute lymphoblastic leukemia (T-ALL). Methods To explore its possibility as a therapeutic target for T-ALL, we investigated the effect of Notch3 silencing on Jurkat and SupT1 cells using a novel tumor-specific short hairpin RNA (shRNA) driven by survivin promoters. Results We found that downregulated expression of Notch3 correlated with significant apoptosis and inhibition of proliferation. Conclusion These facts suggest that downregulating expression of Notch3 could attenuate the Notch signaling activity in T-ALL. All these results indicate that inhibition of Notch3 expression can result in potent antitumor activity in T-ALL.

This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon the result of a single slicer, an efficient architecture named reduced-slicer partial-response DFE (RS-PRDFE) receiver is proposed. The RS-PRDFE receiver eliminates redundant or unused slicers from the previous DFE receiver implementations. Both the simulation and measurement results from a 10 Gb/s ADC-based receiver fabricated in 65 nm CMOS technology and multiple backplane channels demonstrate that the RS-PRDFE can achieve the BER of a 3-4-bit uniform ADC only with 4 data slicers. Also, the combined use of linear equalizers (LEs) can further reduce the required slicer count in RS-PRDFE receivers, but only when the LEs are realized in analog domain.

Accurate analysis of link performance including deterministic and random effects as well as advanced signal conditioning schemes is crucial in modern high-speed I/O design. In recent years, statistical link performance tools such as LinkLab and StatEye are introduced to efficiently analyze the overall link performance with both deterministic and random noise. The statistical-domain analysis has limitations in terms of its capability of accurately simulating system nonlinearity, jitter, as well as coding. In this paper, we present a new hybrid approach that combines statistical and time-domain techniques to efficiently overcome these limitations. The proposed method has several key contributions: 1) capture system nonlinearity; 2) separately simulate short-term deterministic jitter in the time domain and long-term deterministic and random jitter in the statistical domain; 3) co-simulate clock and data channels to capture jitter tracking; and 4) co-simulate signal and power integrity to include simultaneous switching output noise. We demonstrate this hybrid approach by studying the jitter tracking capability of a clock forwarding scheme and the effectiveness of coding in terms of system bit error rate.

Clocked comparators have found widespread use in noise sensitive applications including analog-to-digital converters, wireline receivers, and memory bit-line detectors. However, their nonlinear, time-varying dynamics resulting in discrete output levels have discouraged the use of traditional linear time-invariant (LTI) small-signal analysis and noise simulation techniques. This paper describes a linear, time-varying (LTV) model of clock comparators that can accurately predict the decision error probability without resorting to more general stochastic system models. The LTV analysis framework in conjunction with the linear, periodically time-varying (LPTV) simulation algorithms available from RF circuit simulators can provide insights into the intrinsic sampling and decision operations of clock comparators and the major contribution sources to random decision errors. Two comparators are simulated and compared with laboratory measurements. A 90-nm CMOS comparator is measured to have an equivalent input-referred random noise of 0.73 mVrms for dc inputs, matching simulation results with a short channel excess noise factor ? = 2.

High-speed input/output (I/O) link performance is limited by random noise as well as signal integrity issues such as dispersion, reflections, and crosstalk. Hence, accurate prediction of system performance including these random and deterministic noise is crucial in high-speed link design. This paper presents a novel, fast, and accurate method to simulate the time-domain system response. The presented method calculates the system response using multiple edge responses (MER) based on linear superposition. Being able to take into account system nonlinearity more accurately, the presented method significantly improves simulation accuracy compared with the other published fast simulation techniques based on either single bit response (SBR) or double edge responses (DER), while at the same time maintaining equivalent numerical efficiency. Furthermore, peak distortion analysis, which is commonly used to find the worst-case data pattern based on SBR, is extended for DER and MER using dynamic programming. A multiphase worst-case data pattern approach is also introduced in this paper in order to determine the worst-case system performance under both timing and voltage consideration.

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.

We consider the problem of l∞ optimal deconvolution arising in high data-rate communication between integrated circuits. The optimal deconvolver can be found by solving a linear program for which we use Mehrotra's interior-point approach. The critical step is solving the linear system for the normal equations in each iteration. We show that this linear system has a special block structure that can be exploited to obtain a fast solution technique whose overall computational cost depends mostly on the number of design variables, and only linearly on the number of constraints. Numerical experiments validate our findings and illustrate the merits of our approach. Copyright © 2007 John Wiley & Sons, Ltd.

A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.

A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding

The power integrity characterization of a high-capacity, compute-server memory system operating at 4.8Gbps-per-link is presented. The design robustness of the low-swing, single-ended signaling is verified as the system has excellent immunity to the noise from simultaneously switching outputs (SSO) and a low power-supply-induced jitter (PSIJ) at the primary chip-package resonance frequency.

An innovated low-power memory interface with data rate up to 4.3Gbps presents unique challenges to power integrity (PI) design and verification. While benign to power saving, the employed low-power design techniques, such as power state management, low-power clocking circuit, and on-chip voltage regulator, make the interface more susceptible to supply noise, particularly, in terms of its jitter impact. A systematic approach of analyzing power supply noise induced jitter (PSIJ) at design stage is critical to ensure the robustness of such low-power interface. In this paper, the methodology and simulation results are presented in concert with the correlation data. It is shown that when in fully active state, the steady-state on-chip supply noise is 4mVpp and its PSIJ timing impact is 1.7%UI for the 4.3Gbps operation. However, during power state transition the transient supply noise deteriorates to more than 20mVpp and the corresponding PSIJ impact is as high as 11.3%UI.

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate −13dB mode conversion on both differential pairs at 5Gb/s.

High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The analysis includes on-chip jitter accumulation and link-level jitter tracking by considering both passive channel and on-chip signal path. On-chip measurement techniques which allow in-situ testing of the overall link margin are also described.

As data rate pushes to 10Gbps and beyond, timing jitter has become one of the major factors that limit the link performance. Thorough understanding of the link jitter characteristics and accurate modeling of their impact on link performance is a must even at early design stage. This paper discusses the characteristics of timing jitter in typical I/O interfaces and overviews various jitter modeling methods proposed in the literature during the past few years. Recommendations are given based on the characteristics of timing jitter and their locations.

A 5Gb/s signaling system was designed and fabricated in TSMC's 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution via embedded clocking with superposition of clock in the common-mode was also explored.

This paper demonstrates that the steady-state and adjoint sensitivity analyses can be extended to stochastic mixed-signal systems based on Markov chain models. The examples of such systems include digital phase-locked loops and delta-sigma data converters, of which steady-state response is statistical in nature, consisting of an ensemble of waveforms with probability distribution. For efficient Markov-chain analysis, the paper describes three methods that can limit the number of states: a state discretization scheme based on Gaussian decomposition, a state exploration algorithm that discovers the recurrent states, and a state truncation algorithm that eliminates the states with negligible stationary probabilities. The stochastic AC analysis is performed by deriving a first-order ordinary differential equation governing the perturbations in the stationary probabilities and solving it via phasor analysis. In the digital PLL and first-order ΔΣ ADC examples, the number of states was reduced by a factor of 35 and the frequency-domain phase and noise transfer functions were simulated with a 57~22,000x speed-up compared to using transient, Monte-Carlo simulations.