171 results on '"Jiang, Iris Hui-Ru"'
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2. DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing
3. OpenMPL: An Open Source Layout Decomposer
4. Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops
5. Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack Dependency
6. Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization
7. Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective
8. Graph-Based Deadlock Analysis and Prevention for Robust Intelligent Intersection Management
9. Introduction to the Special Section on Advances in Physical Design Automation
10. Lightning Talk: All Routes to Timing Closure
11. EDA for Domain Specific Computing
12. PV Inverter Control Algorithm Using Reinforcement Learning to Mitigate the Duck Curve Problem
13. Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning
14. Timing macro modeling with graph neural networks
15. Deadlock Resolution for Intelligent Intersection Management with Changeable Trajectories
16. Novel methodology for SRAF placement over a machine learning generated probability map
17. Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines
18. Intelligent Design Automation for Heterogeneous Integration
19. Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering
20. Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets
21. Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval
22. DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper
23. OpenMPL: An Open-Source Layout Decomposer
24. Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials
25. Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles
26. Opportunities for 2.5/3D Heterogeneous SoC Integration
27. Session details: Session 11: Third Keynote
28. DATC RDF-2020
29. Dynamic IR-drop ECO optimization by cell movement with current waveform staggering and machine learning guidance
30. Intelligent design automation for 2.5/3D heterogeneous SoC integration
31. A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles
32. Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization
33. Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems
34. Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures
35. Session details: Keynote 3
36. Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability
37. DATC RDF-2019: Towards a Complete Academic Reference Design Flow
38. Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles
39. OpenMPL: An Open Source Layout Decomposer: Invited Paper
40. Novel methodology for SRAF placement over a machine learning generated probability map
41. Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials
42. Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
43. Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement
44. Efficient search of layout hotspot patterns for matching SEM images using multilevel pixelation
45. DATC RDF
46. iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation.
47. OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing
48. Timing Macro Modeling for Efficient Hierarchical Timing Analysis
49. Recent Research and Challenges in Multiple Patterning Layout Decomposition
50. COSAT
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