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At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

In this work, a novel strategy of colorimetric and photothermal dual-mode sensing determination of ascorbic acid (AA) based on a Ag

By employing a 355-nm nanosecond (ns) ultraviolet (UV) laser annealing, the impact of fluorine (F) co-doping on the formation of a highly activated N-type shallow junction in germanium (Ge) is investigated. Secondary ion mass spectrometry (SIMS) depth profiling of phosphorus (P) demonstrated that an ultra high P concentration of 9 × 1020 cm−3 at a shallow junction of 55 nm with less dopant diffusion can be obtained using ns laser annealing. F co-doping was confirmed to be an efficient way to improve the activation of the P dopants, but show less influence on the redistribution of P dopants within the NLA melted region. However, the activation level of the shallow junction could be increased to approximately 1 × 1020 cm−3 in the presence of F at an optimized concentration.

This work presents a novel process to manufacture advanced Germanium-On-Insulator with integrated Silicon Nitride (GOIN) stripes as light waveguide for Ge photonic devices. Through the integration of GOIN stripes, larger tensile strain could be imposed to the bonded Ge layer which may could be used to tailor the bandgap of Ge material for short wave length infrared application. The successful fabrication of advanced GOIN substrate makes the opportunity for monolithic integration of high-performance Ge-based high mobility transistors with photonic components where silicon nitride is the waveguide with low optical loss.

This paper discussed the limitation of the laser-induced incandescence (LII) method for the measurement of soot in different laminar pulverized coal flames and explored the soot formation character...

The quality of the contact is key for the performance enhancement of the MoS2 device. As the oxygen plasma treatment is developed in the fabrication of MoS2 field effect transistor (FET), we demonstrate that the tunneling layer (MoO3) is formed on the top of the MoS2 contact region and the process induced organic residues in the source and drain regions is effectively removed. The formation of MoO3 can degrade the Fermi level pinning effect at the MoS2/metal interface and lowering the Schottky barrier height. And the flatness of the interface has been greatly improved, with the roughness reduced from 0.53 to 0.166 nm. In this paper, we improve the device performance with an on-/off-current ratio increase by four orders of magnitude, a mobility increase by 10 times at room temperature and the 33-fold decrease in contact resistance. This research shows that oxygen plasma treatment is a promising method for the integration of MoS2 FET in the future.

CVD molybdenum disulfide (MoS2) is shown to chemically oxidize rapidly after pure oxygen plasma bombardment. Atomic force microscopy (AFM), photoluminescence spectrum (PL), Raman spectrum and X-ray photoelectron spectroscopy (XPS) are employed to characterize the physical and chemical properties and indicate that MoO3 is easily formed from MoS2. The result of AFM shows that thickness of the film increases from 0.9 to 1.79 nm after oxygen plasma treatment, which is mainly due to the difference in lattice structure between pristine MoS2 and generated MoO3. XPS analysis shows that the intensity of the S2s peak is reduced to 0 after oxygen plasma treatment. Also, the intensities of Mo4+ peaks disappear at 233.2 eV and 230 eV, leaving only the Mo6+ peaks at 232.5 eV and 235.65 eV, which strongly proves the transformation of MoS2 to MoO3. Further, we use oxygen plasma to treat few-layer MoS2, and find that the top oxidized layer can protect the lower MoS2 from further oxidation. Finally, we obtain p-type doped transistors with this method.

Attribute amnesia (AA) is a recently reported phenomenon whereby participants are unable to report a salient attribute of a stimulus (e.g., the color or identity of a target letter) on which their attention has just been focused during a prior task. This counterintuitive effect has been repeatedly replicated with various simple stimuli such as digits and letters. The current study sought to explore boundaries of AA by investigating whether the phenomenon persists when participants encounter complex, meaningful stimuli (e.g., pictures) that have been shown to hold an advantage in cognitive processing and memory. In Experiments 1a-d, we examined whether AA was observed with different types of complex stimuli. In Experiments 2a-b and 3a-b, we linked the type of stimuli (simple vs. complex and meaningful stimuli) to the other two potential boundary factors of AA (i.e., repetitiveness of target stimulus and set effects of Einstellung) to see whether there were interactions between stimuli type and these two boundary factors. The results demonstrated that the AA effect was still consistently observed for complex stimuli in a typical AA paradigm wherein participants encountered many trials and the targets were repeated across trials. However, this effect only appeared for simple stimuli, but not for complex stimuli in two special cases: when target stimuli were never repeated through the experiment, or when the surprise test was placed on the first trial of the experiment. These findings have crucial implications in understanding the boundaries of the AA phenomenon.

In this work, a novel method consisting of side-wall passivation and a top-metal reveal process is proposed for spintronics devices based on magnetic tunnel junctions (MTJs). The method can efficiently protect ferromagnetic metals and magnesium oxide, which are the key materials of MTJs, and effectively establish electrical contact with the interconnect metals for perpendicular MTJs (p-MTJs). The scheme consists of the passivation of MTJs with dual dielectrics – silicon nitride and silicon oxide – followed by planarization and selective wet etching. The proposed integration scheme was successfully demonstrated with 80-nm-diameter p-MTJ devices.

To allow the use of molybdenum disulfide (MoS2) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS2 transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS2 device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS2 transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 106. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.

Since defects such as traps and oxygen vacancies exist in dielectrics, it is difficult to fabricate a high-performance MoS2 field-effect transistor (FET) using atomic layer deposition (ALD) Al2O3 as the gate dielectric layer. In this paper, NH3 in situ doping, a process treatment approach during ALD growth of Al2O3, is used to decrease these defects for better device characteristics. MoS2 FET has been well fabricated with this technique and the effect of different NH3 in situ doping sequences in the growth cycle has been investigated in detail. Compared with counterparts, those devices with NH3 in situ doping demonstrate obvious performance enhancements: I on/I off is improved by one order of magnitude, from 1.33 × 105 to 3.56 × 106, the threshold voltage shifts from –0.74 V to –0.12 V and a small subthreshold swing of 105 mV/dec is achieved. The improved MoS2 FET performance is attributed to nitrogen doping by the introduction of NH3 during the Al2O3 ALD growth process, which leads to a reduction in the surface roughness of the dielectric layer and the repair of oxygen vacancies in the Al2O3 layer. Furthermore, the MoS2 FET processed by in situ NH3 doping after the Al and O precursor filling cycles demonstrates the best performance; this may be because the final NH3 doping after film growth restores more oxygen vacancies to screen more charge scattering in the MoS2 channel. The reported method provides a promising way to reduce charge scattering in carrier transport for high-performance MoS2 devices.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm−2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was −0.34%, meanwhile, the TDD and RMS surface roughness were 2 × 106 cm−2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

To achieve high device performance and high reliability for the gallium nitride (GaN)-based high electron mobility transistors (HEMTs), efficient heat dissipation is important but remains challenging. Enormous efforts have been made to transfer a GaN device layer onto a diamond substrate with a high thermal conductivity by bonding. In this work, two GaN-diamond bonded composites are prepared via modified surface activated bonding (SAB) at room temperature with silicon interlayers of different thicknesses (15 nm and 22 nm). Before and after post-annealing process at 800 oC, thermal boundary conductance (TBC) across the bonded interface including the interlayer and the stress of GaN layer are investigated by time-domain thermoreflectance and Raman spectroscopy, respectively. After bonding, the 15 nm Si interlayer achieved a higher TBC. The post-annealing significantly increased the TBC of both interfaces, while the TBC of 22 nm silicon interlayer increased greater and became higher than that of 15 nm. Detailed investigation of the microstructure and composition of the interfaces were carried out to understand the difference in interfacial thermal conduction. The obtained stress was no more than 230 MPa for both before and after the annealing, and this high thermal stability of the bonded composites indicates that the room temperature bonding can realize a GaN-on-diamond template suitable for further epitaxial growth or device process. This work brings a novel strategy of SAB followed by high-temperature annealing to fabricate a GaN-on-diamond device with a high TBC.

In this paper, we explored a method to remove the contamination and impurities left on SiC surface after plasma-etched process. The stubborn contamination is resulting from fluorochemical caused by plasma-etched process, residue left after stripping Ni metal mask, Ni–O compounds formed by the metal mask with SiC Si surface oxide film and carbon-containing contamination introduced by the process environment. By adding a layer of SiO2 mask between SiC and the original metal mask together with ultrasonic cleaning and oxygen plasma cleaning process, the sample surface roughness was effectively reduced from 1.090 to 0.055 nm. Moreover, this method supplies a valuable reference for solving the problem of surface contamination caused by plasma etched.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

An approach for improving sidewall roughness of high-aspect-ratio trench is developed. This method relies on the aspect ratio dependent scalloping attenuation (ARDSA) effect in Bosch process, employs reactive ion etching (RIE) process to avoid the rippled sidewall at the top of the trench, while retains Bosch process with increasing trench depth. As both the RIE and Bosch processes are recognized production techniques, this method is easy to implement. Compared with standard Bosch process, the maximum root mean square (RMS) roughness of the sidewall is brought down from 15.1 nm to 6.89 nm.

Electron tunneling through a single magnetic barrier in a HgTe topological insulator has been theoretically investigated. We find that the perpendicular magnetic field would not lead to spin-flip of the edge states due to the conservation of the angular moment. By tuning the magnetic field and the Fermi energy, the edge channels can be transited from switch-on states to switch-off states and the current from unpolarized states can be filtered to fully spin polarized states. These features offer us an efficient way to control charge/spin transport in a HgTe/CdTe quantum well, and pave a way to construct the nanoelectronic devices utilizing the topological edge states.

We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around nanosheet field effect transistor for 5-nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses: (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions; (2) Kubo-greenwood model for low field mobility with considering surface roughness and stress; (3) multisub-band Boltzmann transport equation based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics; and (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5-nm node pMOS, and Si is still promising for nMOS due to strong quantum confinement in Ge channel.

Failing to remember the source of retrievable information is known as source amnesia. This phenomenon has been extensively investigated in long-term memory but rarely in working memory, as we share the intuition that the source information of an item that we have encountered in the immediate past is always available. However, a recent study (Chen, Carlson, & Wyble, 2018) challenged this common sense by showing the source amnesia for simple visual stimuli (e.g., colored square) in the context of working memory when participants did not expect having to report source information, which indicated that the source information of visual stimuli was not automatically encoded into working memory. The current study sought to further examine this newly discovered phenomenon by testing whether it persists with complex and meaningful stimuli in the visual modality (Experiments 1, 4a & 4b), cross-visual-and-auditory modalities (Experiments 2a & 2b), and within-auditory modality (Experiment 3). Interestingly, the results revealed that short-term source amnesia was a robust effect in the visual modality even for complex and meaningful stimuli, whereas it was absent in the cross-visual-and-auditory or within-auditory modalities, regardless of reporting expectation. This indicates differences in working memory representations of visual and auditory stimuli, namely, the representation of auditory stimuli was stored together with the corresponding original sources, while that of visual stimuli was stored independently of its source information. These findings have crucial implications for further clarifying the longstanding debate regarding whether or not there is a modality-independent working memory storage system for different modalities.

In this paper, a near-ideal subthreshold swing MoS

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy, the start point of the experiments includes Stranski–Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it’s threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm−2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

We investigate theoretically the electron transport through (001) HgTe/CdTe quantum well heterostructures with inverted-band in planar geometry, where Dirac-like spin–momentum locked interface states have been predicted to be formed and topologically protected against perturbations preserving time-reversal symmetry. In this work, k.p theory and scattering matrix method are used to characterize the interface states of the (001) HgTe/CdTe heterostructure as well as to understand the influence of external electric fields. We find distinct features of the transmission and conductance by considering both Rashba and Dresselhuas spin–orbit interactions. The efficient spin–flip conversion between spin-up and spin-down channels are found by tuning the strength of Rashba and Dresselhuas spin–orbit interactions. It is shown that ideal spin–flip efficiency, i.e., the complete spin–flip, can be achieved with specific spin–orbit coupling strengths. This spin–flip mechanism provides us a realistic way to manipulate the spin orientation which can be constructed low-power information processing device. Furthermore, we address the topological edge states induced unique spin manipulation capability by comparing with the conventional electron transport properties in bulk states. In addition, we analyze the transport behavior when the system in the presence of Zeeman term which may play an important role for a high magnetic field in a realistic experimental setup.

Energy band lineup at hetero-interface and its physical origin have been always a fascinating issue, and are being intensely investigated. The understanding of the influence of an interlayer on the band lineup of hetero-interface provides a view of studying the band lineup of hetero-interface. Thus in this paper, the Al2O3/GeOx/Ge structure is employed, and the effect of interlayer GeOx thickness on band lineup of Al2O3/GeOx/Ge structure is studied by X-ray photoelectron spectroscopy technique. The valence band offset of Al2O3/Ge hetero-interface is found to be nearly identical (3.5 eV) for different GeOx thicknesses (0.2 nm ~ 1.2 nm). The gap states model is employed to successfully explain these results. The interfacial dipole in Al2O3/GeOx/Ge structure is nearly unchanged with GeOx thickness based on the gap states model. This indicates that the band lineup of Al2O3/GeOx/Ge structure is independent on GeOx thickness. Thus these further verify that the gap state model is feasible in elucidating energy band lineup at hetero-interfaces.

In this work, tantalum nitride (TaN) was chosen as the wet etch stop layer (WESL) for its application in the 22 nm and beyond nodes CMOS technology. TaN WESL prevents the attacking of titanium nitride (TiN)/hafnium dioxide (HfO 2 ) stack covering n-channel MOS (nMOS) regions from selectively stripping work function metals of p-channel MOS (pMOS) gate, i.e. TiN & titanium (Ti), by ammonia hydrogen peroxide mixture (APM) solution. In terms of etching selectivity to TiN & Ti, gate filling capability and work function tuning for both nMOS and pMOS, the properties of TaN films prepared by different methods such as physical vapor deposition (PVD) and atomic layer deposition (ALD) were investigated systematically.

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB.