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This article presents two millimeter-wave frequency reconfigurable dual-band CMOS power amplifiers (PAs) for fifth-generation (5G) communications comprising a single-stage dual-band PA and a two-stage dual-band PA for higher gain. The PAs cover multiple 5G communication bands, n257 (26.5-29.5 GHz) and n260 (37-40 GHz), which use reconfigurable transmission line transformers (TLTs) for output, input, and interstage matching networks. These matching networks allow the operating frequency bands to be changed, thereby achieving optimum performance. The integrated mode selection switches in the transformers reconfigure the inductances of the TLTs to cover two frequency bands, which allows the PAs to have small overall chip sizes. These are fabricated in a 28-nm bulk CMOS process. The single-stage dual-band PA achieves 20.2-/19.1-dBm saturated output power ( ${P}_{sat}$ ), 18.7-/18.6-dBm 1-dB compressed output power ( ${P}_{1 dB}$ ), and 33.6%/32% peak power-added efficiency (PAE) at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.11 mm². The two-stage dual-band PA achieves 19.1-/19.5-dBm ${P}_{sat}$ , 17-/17.8-dBm ${P}_{1 dB}$ , and 31.3%/30.5% PAE at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.165 mm². Both PAs are tested under 64-quadrature amplitude modulation signals with a 100-MHz channel bandwidth. The single-stage PA achieves 14.7- and 12.3-dBm average output powers ( ${P}_{avg}$ ) with -25.1- and -25-dB error vector magnitudes (EVMs) at 26.5 and 37 GHz, respectively. The two-stage PA achieves 12.3- and 11.6-dBm ${P}_{avg}$ 's with -25.3- and -25.1-dB EVMs at 26.5 and 37 GHz, respectively.

This paper presents a two-chip supply modulation architecture for efficient RF power amplification using a fully switched-mode supply modulator (SM) and a linear-assisted hybrid SM to support simultaneous transmission on LTE and 5G bands. The designed fully switched-mode SM consists of a fast buck converter and a slow buck converter, and it achieves 88.2% peak efficiency with a low RX band noise of -140dBm/Hz at the SM output. The designed 5G NR SM, consisting of a class-AB linear amplifier (LA) and an interleaved 3-level buck-boost converter provides a 150-MHz 3-dB bandwidth for tracking the 100-MHz envelope signal. An optimal RF-PA supply deployment using the two SMs efficiently supports multiple RF-PA loads while satisfying the dual transmission requirements of E-UTRAN New Radio Dual-Connectivity (EN-DC) and 5G 100-MHz ET operation.

This paper presents a highly efficient 5G NR RF transmitter (TX) system consisting of a SAW-less RF transmitter IC, an RF power amplifier module (PAM) and a supply modulator IC (SM-IC). The RF TX with a 12-bit current-steering digital-to-analog converter (DAC) generates +7 dBm of output power to drive the PAM for high power user equipment (HPUE) in the 5G NR n77 band. The SM-IC generates a maximum output power of 10W at a 5-V peak envelope output voltage and provides an envelope tracking supply voltage of a 100-MHz NR signal to the n77 PAM. The PAM employing a differential topology generates a saturation output power of 32.5 dBm including the loss of the SOI switch and output filter. The designed PAM in ET mode achieves an ACLR of -37 dBc at a 27-dBm output power and saves 950 mW in comparison to APT mode.

This paper presents 2G/3G/4G/5G transmitter that has a compact die area and supports multi bands in 5G new radio (NR). The transmitter with inter-digitated switchable transformer is designed to support n77/n78/n79 of 5G FR1 bands (3.2GHz to 5GHz) and B46/B47 of V2X bands (5.125GHz to 5.925GHz). The transformer provides optimum transformed load impedance at the drive amplifier output with 3-stacked switches. The on-chip transformer with inter-digitated structure results in a high coupling factor to minimize the insertion loss. An interstage matching network between a mixer and a drive amplifier induces a channel flatness characteristic. The designed transmitter is fabricated using a 14nm FinFET CMOS process. It achieves a peak average output power of 7dBm and 2% under measured root mean square (rms) EVM in the case of DFT-s-OFDM 256QAM Full-RB signal, while satisfying the 3GPP specification. It also satisfies 1dB under channel flatness and the adjacent channel leakage ratio (ACLR) −43.2dBc in case of n77/n78, and −42.7dBc in case of n79, while consuming 295mW and 300mW dc power at 7.5dBm and 6.7dBm output power, respectively. The transmitter with inter-digitated switchable transformer has a size of 0.18mm2.

A frequency reconfigurable dual-band power amplifier (PA) with reconfigurable transmission line transformers (TLT) is presented, which can be operated at both the n257 (26.5-29.5 GHz) and n260 (37–40 GHz) 5G communication bands. The PA utilizes reconfigurable TLTs for output and input matching networks to reconfigure the PA between the n257 and n260 bands with optimal performance in both bands. The reconfigurable TLTs provide frequency reconfigurability to the PA by changing both the primary and secondary side inductances of the TLTs. The switches for the TLTs are located in the space inside the TLTs, which results in a small overall chip area. The dual-band PA is fabricated using a 28-nm bulk CMOS process. It achieves 20.2 and 19.1 dBm saturated output powers, 18.7 and 18.6 dBm 1-dB compressed output powers and 33.6% and 32% peak power added efficiencies at 26.5 and 37 GHz, respectively. The dual-band PA has a core size of 0.11 mm2.

Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 \Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.

This paper presents a hybrid supply modulator (SM) including a buck-boost (BB) converter, which has wide battery operating range for cellular envelope tracking (ET) applications. The proposed SM supports both ET and average power tracking (APT) mode depending on the power amplifier (PA) output power level. The output voltage swing of SM is boosted up to 4.5 V by the integrated BB converter as a supply of a linear amplifier. The dynamic-controlled BB output increases ET operating range, whose efficiency is higher than that of APT, by scaling down the supply voltage of the linear amplifier according to the PA output power level. A selective supply voltage of a switching amplifier and a reverse current sensing circuit are employed to prevent the reverse current through the power inductor of the switching amplifier. The proposed automatic current ratio controller between the linear amplifier and the switching amplifier provides the robust performance against the battery voltage variation of 3.2–4.6 V. A programmable bias current of the class-AB output buffer and a programmable hysteretic comparator are employed to achieve the optimum efficiency and bandwidth depending on the operating signal bandwidth. Optimal control for low signal bandwidth applications such as voice over Long-Term Evolution (LTE) with the selective notch filter provides the maximum efficiency of 88.2% with −135 dBm/Hz output noise. The proposed SM supports the LTE 20-MHz envelope signal with 78% efficiency at 800-mW output. Adapting the designed SM to frequency-division duplex Band3 radio frequency PA, the implemented ET-PA achieves the power added efficiency of 41.6% at 27-dBm PA output power while achieving −40 dBc of E-UTRA ACLR and −137 dBm/Hz of receiver band noise. The chip is implemented in the 0.13- $\mu \text{m}$ CMOS process, and the die size is 5 mm2.

In recent years, buck-boost converters have been widely utilized for battery-powered mobile systems such as RF power amplifiers, battery chargers, and LED drivers. However, in a wide battery voltage range, they face challenges including dynamic voltage scaling (DVS), wide load current range, and dynamic line/load transients while ensuring reliability for an industrial usage. To resolve these issues, the conventional buck-boost (CBB) converter should overcome the characteristic of discontinuity in the output transfer current (OTC) which causes degradation of loop dynamics and transient response. Several past works with continuous OTC have been proposed to resolve these problems, but their voltage conversion ratios are limited [1], [2]. Moreover, in [3], [4], a high-voltage (HV) process, which necessitates large active area and incurs high fabrication cost, is required to withstand voltage stresses over 10V (2×V IN ) applied across power switches. To overcome the above challenges, this paper proposes a voltage-tolerant three-level buck-boost (TLBB) converter. The TLBB has continuous OTC and uses only normal 5V CMOS devices for its switches. In addition, a voltage-tolerant dual channel-interleaved three-level buck-boost (DTLBB) converter is suggested for applications [5] requiring a wide range of load current and high conversion ratio while supporting fast DVS transition.

To assess the risk of fumonisin contamination in Korean cereals, we isolated colonies of the Fusarium fujikuroi species complex (FFSC) from barley, maize, rice and soybean samples from 2011 to 2015. A total of 878 FFSC strains were isolated mostly from maize and rice, and species identity of the isolates were determined using the DNA sequence of the translation elongation factor 1-α (TEF-1α) and RNA polymerase II (RPB2) genes. Fusaria recovered from Korean cereals included F. fujikuroi (317 isolates and a frequency of 36%), F. proliferatum (212 isolates and 24.1%), F. verticillioides (170 isolates and 19.4%), F. concentricum (86 strains and 9.8%), F. andiyazi (56 isolates and 6.4%), F. subglutinans (28 isolates and 3.2%), F. thapsinum (5 isolates and 0.6%), and F. circinatum (2 isolates and 0.2%). The rice samples were dominated by F. fujikuroi (47.4%), F. proliferatum (27.3%), and F. concentricum (15.1%), whereas maize samples were dominated by F. verticillioides (33.9%), F. fujikuroi (25.3%), and F. proliferatum (21.1%). A phylogenetic analysis of 70 representative isolates demonstrated that each species was resolved as genealogically exclusive in the ML tree. Fumonisin production potential was evaluated using a PCR assay for the fumonisin biosynthesis gene, FUM1 in all of the isolates. Most of the isolates tested (94%) were positive for FUM1. All of the isolates assigned to F. fujikuroi, F. proliferatum, F. verticillioides and F. thapsinum were positive for FUM1 irrespective of their host origin. Seventy-seven representative isolates positive for FUM1 were examined for fumonisin production in rice medium. The majority of F. proliferatum (26/27, 96.3%), F. verticillioides (16/17, 94.1%) and F. fujikuroi (19/25, 76.0%) produced both FB1 and FB2. Notably, 16 of 19 fumonisin-producing F. fujikuroi produced >1000μg/g of fumonisins (FB1+FB2) in rice medium, which is higher than that in previous reports. These results suggest that F. fujikuroi can produce high levels of fumonisins similar to F. verticillioides and F. proliferatum.

The 5G-New-Radio (NR) standard in millimeter wave (mm-wave) bands requires a low-cost antenna module consisting of a phased-array transceiver with beamforming [1], an antenna array, and a power management IC (PMIC). Since a typical on-chip mm-wave CMOS power-amplifier (PA) arrays have poor power efficiency due to the lossy substrate and the low maximum available-gain frequency of CMOS processes, they cause serious thermal issues due to the high power density and reduce battery life in a mobile handset. Recently, supply-modulation (SM) techniques, such as an envelope tracking (ET) and an average-power tracking (APT) instead of a direct battery-connected supply, have been introduced to enhance PA efficiency [2]. However, these techniques have few challenges, such as limited ET tracking bandwidth and APT transition time, to support new requirements of the 5G NR standard. In order to manage the power effectively of a phased-array module, a special SM technique named symbol-power tracking (SPT) is proposed for the power management in this work. The SPT controls the supply voltage of mm-wave PA arrays every few micro-second (symbol to symbol), which is much faster than that of APT, which adjusts the output voltage every one millisecond (sub-frame to sub-frame).

In the recent 3GPP standard, 5G New Radio (NR) in the sub-6GHz frequency band supports up to 100MHz bandwidth (BW) for uplink channel and requires fast on/off transition below $10 \mu \mathrm {s}$ to support short transition-time interval (TTI). Thus, it forces the supply modulator (SM) to track the NR-100MHz envelope signal for power saving of an RF power amplifier (RF-PA) and requires a fast dynamic voltage-scaling (DVS) transition. For the 3G/LTE uplink, the SM has to satisfy low receiver-band noise (RxBN) for LTE-FDD bands [1] and a boosted output for Power Class 2 high-power user equipment (HPUE) in TD-LTE [2], [3]. In order to support the 100MHz envelope tracking (ET) BW, the SM must have a 3dB bandwidth of at least 125MHz while keeping sufficient phase margin in the presence of few-hundred-pF load capacitance. Furthermore, a typical linear-assisted SM topology has maximum efficiency limitation due to the AB bias current, sinking- and sourcing-current of the linear amplifier. In this work, a voltage-buffer-compensated (VBC) Class-AB linear amplifier (LA) and a feed-forward fast-switching (FFFS) buck converter are proposed to achieve the 100MHz ET BW and high system-power efficiency.

Fusarium graminearum species complex (FGSC) causes Fusarium head blight in small grain cereals. To date, four species (F. graminearum, F. asiaticum, F. boothii, and F. meridionale ) belonging to FGSC frequently occur in Korean cereals. In addition, we first reported the occurrence of additional species (F. vorosii ) within FGSC, which was isolated from barley, corn, and rice in Korea. Phylogenetic analysis of the Fusarium isolates of this group using combined multi-gene sequences confirmed species identification. Moreover, the macroconidia produced by these isolates were morphologically similar to those of the F. vorosii holotype. Chemical analysis indicated that the F. vorosii isolates produced various trichothecenes such as nivalenol and deoxynivalenol with their acetyl derivatives along with zearalenone. Pathogenicity tests demonstrated that all of the F. vorosii isolates examined were pathogenic on barley, corn, and rice with variation in aggressiveness. This study is the first report of F. vorosii in Korean cereals, their pathogenicity towards barley and corn, and their ability to produce trichothecenes and zearalenone.

Uplink carrier aggregation (UL-CA) and high-power user equipment (HPUE) are proposed in the recent 3GPP standard [1]. UL-CA increases data-rate by aggregating intra-or inter-band carriers, and requires a supply modulator (SM) IC to generate two independently modulated supply voltages for the separate transmitter (TX) paths. Power Class 2, a new HPUE standard intended for TD-LTE Band41, allows 26dBm output power, which is 3dB higher than typical Power Class 3. To achieve 26dBm output, an SM must provide an RF power amplifier (PA) with larger current and boosted voltage above battery range. However, conventional Sm-ICs support only Power Class 3 PAs with intra-band contiguous CA up to 40MHz bandwidth in an envelope-tracking (ET) operation [2]. In order to support non-contiguous intra- and inter-band CA, a typical ET system needs two SMs with double the external components, occupying great PCB area in a cellular handset. This paper presents a single-chip SM-IC with two independently controlled TX outputs supporting Power Class 2. In this way, the SM-IC saves the BOM cost and the PCB area while achieving high system-power efficiency and low receiver-band noise.

A multimode RF amplitude modulator and a digitally controlled variable attenuator (VATT) are presented. A comprehensive analysis of nonlinear distortion in a current source modulated amplitude modulator is studied in this paper. To improve the dynamic range and reduce local oscillator leakage, dual power modes and a cascode transistor for amplitude modulation are employed in the amplitude modulator. The amplitude modulator consists of a switching transistor with a modulating current source, which allows low power consumption and linear amplitude modulation. The digitally controlled VATT is designed for power level control. Five II stages are cascaded to attain the attenuation levels over 32 dB. By using the proposed adaptive II type attenuator, we can get the optimized attenuation stages and port matching at all the attenuation states. The maximum output power of the modulator is 7.8 dBm, while consuming 18 mA of dc current. In the low power mode, the modulator consumes less than 1 mA of dc current. The current consumption is scaled down to 7 mA when the modulated WCDMA signal output power is 0.9 dBm and the EDGE signal output power is 1.2 dBm. The measured minimum insertion loss of the VATT is 2.5 dB and the maximum attenuation control range is 34.8 dB at 1.95 GHz. The control resolution is 1 dB. The worst caseS11 and S22 responses were measured to be -16 dB. There is no power consumption at the VATT. The chip is implemented with a 0.18-μm CMOS process. The total chip size is 1 × 0.9 mm2.

For achieving boost capability and wideband with high efficiency in Envelope Modulator (EM), a newly proposed topology is introduced in this paper. The proposed EM consists of two converters: one is Low Frequency Converter (LFC) with Single Inductor Dual Output (SIDO) and the other is High Frequency Converter (HFC) with wideband capability. The two converters are combined directly in parallel without AC coupling capacitor by employing Low Frequency Current Balancing (LFCB) technique. The chip is implemented in 0.18μm CMOS process achieving 86.55% peak efficiency while tracking a 10MHz LTE envelope signal.

Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].

This letter presents an injection-locked CMOS power amplifier for pulse width modulation (PWM) digitized polar transmitter. A power oscillator combined with injection-locking technique reduces the required driving power and provide high drain efficiency in the power stage. The switched power oscillator is proposed for PWM digitized polar transmitter. To achieve differential to single output and impedance transformation, a lumped element balun, employing a minimum number of discrete components, is used. The power amplifier achieved a power-added efficiency of 70.7% at a maximum output power of 29.05 dBm. The measured drain efficiency in the power stage was 72.7% at 820 MHz. The chip is implemented with a 0.18 μm CMOS process. The total chip size is 0.48 mm2.

A power up-mixer is proposed in this letter. A merged CMOS linear power amplifier (PA) and mixer allows low current consumption and smaller chip size than a conventional integrated transmitter including a mixer and a CMOS linear PA. The chip is fabricated in a 0.18 mum CMOS process and in an integrated-passive-device. Measurements show a drain efficiency of 27% at 27.2 dBm of 1 dB compression point (P1dB) output power from 1.75 to 1.95 GHz. Power conversion gain is 26.4 dB and LO leakage is -43 dBc.

This paper presents a digitally controlled envelope modulator with low code-AM distortion that can be used as a building block in a digital to RF polar transmitter. The RF envelope signal modulation is performed by digitally controlling the number of activated unit amplifier cells. The phase modulated LO input signal drives a switching transistor gate of the each cell. The 8-bit cell array has 63 unary-weighted cells for MSB 6 bits and 3 segmented unary-weighted cells for LSB 2 bits. Low code-AM distortion is achieved by introducing a current source below the switch transistor in the unit cell. A Class E output matching network is used for the high drain efficiency. The proposed modulator delivers 4.91-dBm peak output power at 970MHz with the power consumption of 28.4mW. An EDGE signal is applied to demonstrate the dynamic operations. It is fabricated in 0.13µm CMOS process and the chip size without pad is 380um Χ770um.

A CMOS switching power amplifier for ΔΣ digitized polar RF transmitter is implemented in 0.18-µm process. A current source is introduced in the proposed switching PA to achieve ΔΣ digitized amplitude modulation. The modulation with the current source is suitable for high speed modulated signal such as an oversampled ΔΣ signal. The PA operates at 910 MHz with the maximum output power of 23.5 dBm and power efficiency of 55.4% at the maximum output power. The maximum output power range with the current source modulation is 31 dB.

A CMOS power amplifier for Multi-mode LINC operation is implemented in 0.18-µm process. The LINC architecture except signal separator was integrated and implemented with two-chip solution. LINC operation is used to increase the maximum linear output power in the saturation range of linear PAs. The designed PA operates at 1950 MHz with the maximum linear output power of 26 dBm with 20% PAE for WCDMA signal. The improvement of 2 dB linear output power and 8% efficiency at the maximum linear power can be obtained by using the multi-mode LINC operation.

An envelope modulator (EM) is presented to increase the efficiency of an RF power amplifier. In order to supply an output voltage higher than the input voltage while providing low-frequency power in the EM, a single-inductor dual-output (SIDO) converter is introduced. By employing the SIDO converter, the EM does not require an additional boost converter. In addition, a high-frequency converter (HFC) with a wide-bandwidth capability is also proposed. These two converters, the SIDO converter and the HFC, are combined in parallel without an ac coupling capacitor by employing a low-frequency current-balancing technique. The chip is implemented in a 0.18-μm CMOS process and achieves 86.5% peak efficiency while tracking a 10-MHz long-term evolution envelope signal.

This paper presents a direct-conversion transceiver technology for full digital DS-UWB applications. It is implemented in 0.18 []m CMOS technology and total current consumption is 143 mA including PLL, VCO. The full chip size is 9 mm2, packaged in MLF 64 pin.