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A gate structure design for negative capacitance field effect transistors (NCFETs) is proposed. The hysteresis loop in current–voltage performances is eliminated by the nonlinear C–V dependence of polysilicon in the gate dielectrics. Design considerations and optimizations to achieve the low SS and hysteresis-free transfer were elaborated. The effects of gate-to-source/drain overlap, channel length scaling, interface trap states and temperature impact on SS are also investigated.

The Ge p-MOSFETs on (110) substrates using two-step implantation and NiGe contacts have been demonstrated. The record peak mobility of 528 ${\rm cm}^{2}/{\rm V}\cdot{\rm s}$ of the (110) Ge device is measured by the spilt $C{-}V$ method and can be further enhanced by proper stress. Ge p-FETs on (110) substrates have lower mobility enhancement than (100) devices under compressive strain along the channel. The peak mobility decreases with decreasing temperature due to impurity scattering. The larger density of interface states causes the larger threshold voltage shift from the room temperature to 100 K as compared with Si MOSFETs.

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

A two-step pseudo isothermal plane model is used to calculate the thermal resistance of BEOL (Rth, beol). The intrinsic thermal resistances of 14nm FinFETs (Rth0, Device) are extracted with face-up (conventional measurement, heat flow from the channel to substrate) and face-down (flip-chip, heat flow from the channel to metal contact) configurations. Since the free convection of air has a large thermal resistance, the heat flow direction affects Rth0, Device. The face-up Rth0, Device is higher than face-down Rth0, Device. This is more significant for multi-finger FinFETs. The volume of hot spot affects the cooling time. In an inverter, the maximum temperature (Tmax) of pFET is higher than nFET due to the low thermal conductivity of SiGe S/D. Tmax and the high temperature duration can be controlled by the current and output capacitive loading of the inverter. The residual temperature in the channel and the temperatures of M1 layer are found too low to reflect the real device temperature, which may lead to an underestimation of device temperature with transient AC input.

Through-silicon via (TSV) induced stress field and device performance variation are investigated using N28 silicon data. Back-end-of-line (BEOL) dielectrics affects the stress field of via-last TSV. Asymmetric keep-out zone (KOZ) is observed, i.e. the absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|). The physics behind the asymmetry is described. A KOZ model considering the asymmetric stress field is proposed and verified by experiment data.

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.

Ge is one of the most promising candidate for p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) because its highest hole mobility than Si and III-V materials. Since the carrier mobility depends on both the substrate orientation and channel direction. The calculation shows that (110) Ge p-MOSFET has the highest unstrained hole mobility with the channel direction. To further improve the performance, the compressive stress is applied mechanically to enhance the hole mobility. The source/drain (S/D) resistance is also reduced using the NiGe contact electrodes.