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As very large-scale integration technology shrinks to fewer tracks per standard cell, e.g., from 10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multibit flip-flops or flop trays to save power creates large cells that further complicate critical design tasks, such as placement. Detailed placement happens to be a key optimization transform, which is repeatedly invoked during the design closure flow to improve design parameters, such as wirelength, timing, and local wiring congestion. Advanced node designs, with hundreds of thousands of multiple-row cells, require a paradigm change for this critical design closure transform. The traditional approach of fixing multiple-row cells during detailed placement and only optimizing the locations of single-row standard cells can no longer obtain appreciable quality of results. It is imperative to have new techniques that can simultaneously optimize both multiple- and single-row height cell locations during detailed placement. In this paper, we propose a new density-aware detailed placer for heterogeneous-sized netlists. Our approach consists of a chain move scheme that generalizes the movement of heterogeneous-sized cells, a nested dynamic programming-based approach for ordered double-row placement and a network flow-based formulation to solve ordered multiple-row placement for wirelength and density optimization. Experimental results demonstrate the effectiveness of these techniques in wirelength minimization and density smoothing compared with the most recent detailed placers for designs with heterogeneous-sized cells.

Electron beam lithography (EBL) is a promising, maskless solution for the technology beyond 14nm logic nodes. To overcome its throughput limitation, industry has proposed character projection (CP) technique, where some complex shapes (characters) can be printed in one shot. Recently, the traditional EBL system was extended into a multi-column cell (MCC) system to further improve the throughput. In an MCC system, several independent CPs are used to further speed-up the writing process. Because of the area constraint of stencil, the MCC system needs to be packed/planned carefully to take advantage of the characters. In this article, we prove that the overlapping aware stencil planning (OSP) problem is NP-hard. Then we propose E-BLOW, a tool to solve the MCC system OSP problem. E-BLOW involves several novel speedup techniques, such as successive relaxation and dynamic programming. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both the conventional EBL system and the MCC system.

Pin access has become one of the most difficult challenges for detailed routing in advanced technology nodes, for example, in 14nm and below, for which double-patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches, such as M2 and M3. Self-aligned double patterning (SADP) provides better control on line edge roughness and overlay, but it has very restrictive design constraints and prefers regular layout patterns. This article presents a comprehensive pin-access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include precomputation of both intracell and intercell pin accessibility, as well as local and global pin-access planning to enable handshaking between standard cell-level pin access and detailed routing under SADP constraints. A pin access–driven rip-up and reroute scheme is proposed to improve the ultimate routability. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

As the feature size of semiconductor process further scales to sub-16 nm technology node, triple patterning lithography (TPL) has been regarded as one of the most promising lithography candidates along with extreme ultraviolet, electron beam lithography, and directly self-assembly. M1 and contact layers, which are usually deployed within standard cells, are the most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement, to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the precoloring solutions of standard cells, we present a TPL aware detailed placement where the layout decomposition and placement can be resolved simultaneously. In addition, we propose a linear dynamic programming to solve TPL aware detailed placement with maximum displacement, which can achieve good trade-off in terms of runtime and performance. Experimental results show that our framework can achieve zero conflict, meanwhile can effectively optimize the stitch number and placement wire-length.

As VLSI technology shrinks to fewer tracks per standard cell, e.g., from 10-track to 7.5-track libraries (and lesser for 7nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multi-bit flip-flops or flop trays to save power creates large cells that further complicate critical design tasks, such as placement. Detailed placement happens to be a key optimization transform, which is repeatedly invoked during the design closure flow to improve design parameters, such as, wirelength, timing, and local wiring congestion. Advanced node designs, with hundreds of thousands of multiple-row cells, require a paradigm change for this critical design closure transform. The traditional approach of fixing multiple-row cells during detailed placement and only optimizing the locations of single-row standard cells can no longer obtain appreciable quality of results. It is imperative to have new techniques that can simultaneously optimize both multiple- and single-row high cell locations during detailed placement. In this paper, we propose a new density-aware detailed placer for heterogeneous-sized netlists. Our approach consists of a chain move scheme that generalizes the movement of heterogeneous-sized cells as well as a nested dynamic programming based approach for wirelength and density optimization. Experimental results demonstrate the effectiveness of these techniques in wirelength minimization and density smoothing compared with the most recent detailed placer for designs with heterogeneous-sized cells.

This paper presents a robust global router called NTHU-Route 2.0 that improves the solution quality and runtime of NTHU-Route by the following enhancements: 1) a new history based cost function; 2) new ordering methods for congested region identification and rip-up and reroute; and 3) two implementation techniques. We report convincing experimental results to show the effectiveness of each individual enhancement. With all these enhancements together, NTHU-Route 2.0 solves all ISPD98 benchmarks with very good quality. Moreover, NTHU-Route 2.0 routes 7 of 8 ISPD07 benchmarks and 12 of 16 ISPD08 benchmarks without any overflow. Compared with other state-of-the-art global routers, NTHU-Route 2.0 is able to produce better solution quality and/or run more efficiently.

Pin access has become one of the most difficult challenges for detailed routing in 14nm technology node and beyond, where double patterning lithography has to be used for manufacturing lower metal layers with tight pitches. Self-aligned double patterning (SADP) provides better control on the line edge roughness and overlay but it has very restrictive design constraints and prefers regular layout patterns. This paper presents a comprehensive pin access planning and regular routing framework (PARR) for SADP friendliness. Our key techniques include pre-computation of both intra-cell and inter-cell pin accessibility, as well as local and global pin access planning to enable the handshaking between standard cell level pin access and detailed routing under SADP constraints. Our experimental results demonstrate that PARR can achieve much better routability and overlay control compared with previous approaches.

Unidirectional design has attracted lots of attention with the scaling down of technology nodes. However, due to the limitation of traditional lithography, printing the randomly distributed dense cuts becomes a big challenge for highly scaled unidirectional layout. Recently directed self-assembly (DSA) has emerged as a promising lithography technique candidate for cut manufacturing because of its ability to form small cylinders inside the guiding templates and the actual pattern size can be greatly reduced. In this paper, we perform a comprehensive study on the DSA cut mask optimization problem. We first formulate it as integer linear programming (ILP) to assign cuts to different guiding templates, targeting at minimum conflicts and line-end extensions. As ILP may not be scalable for very large size problem, we further propose a speed-up method to decompose the problem into smaller ones and solve them separately. We then merge and legalize the solutions without much loss of result quality. The proposed approaches can be easily extended to handle more DSA guiding patterns with complicated shapes. Experimental results show that our methods can significantly reduce the total number of unresolvable patterns and the line-end extensions for the targeted layouts.

Under the low-k1 lithography process, lithography hotspot detection and elimination in the physical verification phase have become much more important for reducing the process optimization cost and improving manufacturing yield. This paper proposes a highly accurate and low-false-alarm hotspot detection framework. To define an appropriate and simplified layout feature for classification model training, we propose a novel feature space evaluation index. Furthermore, by applying a robust classifier based on the probability distribution function of layout features, our framework can achieve very high accuracy and almost zero false alarm. The experimental results demonstrate the effectiveness of the proposed method in that our detector outperforms other works in the 2012 ICCAD contest in terms of both accuracy and false alarm.

Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic node. To overcome its throughput limitation, industry has proposed character projection (CP) technique, where some complex shapes (characters) can be printed in one shot. Recently the traditional EBL system is extended into multi-column cell (MCC) system to further improve the throughput. In MCC system, several independent CPs are used to further speed-up the writing process. Because of the area constraint of stencil, MCC system needs to be packed/planned carefully to take advantage of the characters. In this paper, we prove that the overlapping aware stencil planning (OSP) problem is NP-hard. To solve OSP problem in MCC system, we present a tool, E-BLOW, with several novel speedup techniques, such as successive relaxation, dynamic programming, and KD-Tree based clustering. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both conventional EBL system and MCC system., Comment: arXiv admin note: text overlap with arXiv:1402.2435

Optical Proximity Correction (OPC) has been widely adopted for resolution enhancement to achieve nanolithography. However, conventional rule-based and model-based OPCs encounter severe difficulties at advanced technology nodes. Inverse Lithography Technique (ILT) that solves the inverse problem of the imaging system becomes a promising solution for OPC. In this paper, we consider simultaneously 1) the design target optimization under nominal process condition and 2) process window minimization with different process corners, and solve the mask optimization problem based on ILT. The proposed method is tested on 32nm designs released by IBM for the ICCAD 2013 contest. Our optimization is implemented in two modes, MOSAIC_fast and MOSAIC_exact, which outperform the first place winner of the ICCAD 2013 contest by 7% and 11%, respectively.

Due to the delay of EUVL, multiple patterning techniques have been used to extend the 193nm lithography to 22nm/14nm nodes, and possibly further. There are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring conicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay eects. Meanwhile, there are studies showing that it is very important to consider the multiple patterning implications at earlier physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we will show some recent results and propose a unied physical design methodology for standard cell compliance, pin access, routing, and placement to bridge the gap from mask/layout decomposition to physical design, while accommodating various requirements from double/triple patterning lithography in certain \correct by construction" manner.

As technology nodes continues shrinking, layout patterns become more sensitive to lithography processes, resulting in lithography hotspots that need to be identied and eliminated during physical verication. In this paper, we propose an accurate hotspot detection approach based on PCA (principle component analysis)-SVM (support vector machine) classier. Several techniques, including hierarchical data clustering, data balancing, and multi-level training, are provided to enhance performance of the proposed approach. Our approach is accurate and more ecient than conventional time-consuming lithography simulation; in the meanwhile, provides high exibility to adapt to new lithography processes and rules.

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end- cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the con ict number and the stitch number.

Self-aligned double patterning (SADP) has become a promising technique to push pattern resolution limit to sub-22nm technology node. Although SADP provides good overlay controllability, it encounters many challenges in physical design stages to obtain conflict-free layout decomposition. In this paper, we study the impact on placement by different standard cell layout decomposition strategies. We propose a SADP friendly standard cell configuration which provides pre-coloring results for standard cells. These configurations are brought into the placement stage to help ensure layout decomposability and save the extra effort for solving conflicts in later stages.

Advanced lithography techniques enable higher pattern resolution; however, techniques such as extreme ultraviolet lithography and e-beam lithography (EBL) are not yet ready for high volume production. Recently, complementary lithography has become promising, which allows two different lithography processes work together to achieve high quality layout patterns while not increasing much manufacturing cost. In this paper, we present a new layout decomposition framework for self-aligned double patterning and complementary EBL, which considers overlay minimization and EBL throughput optimization simultaneously. We perform conflict elimination by merge-and-cut technique and formulate it as a matching-based problem. The results show that our approach is fast and effective, where all conflicts are solved with minimal overlay error and e-beam utilization.

Layout fracturing is a fundamental step in mask data preparation and e-beam lithography (EBL) writing. To increase EBL throughput, recently a new L-shape writing strategy is proposed, which calls for new L-shape fracturing, versus the conventional rectangular fracturing. Meanwhile, during layout fracturing, one must minimize very small/narrow features, also called slivers, due to manufacturability concern. This paper addresses this new research problem of how to perform L-shaped fracturing with sliver minimization. We propose two novel algorithms. The first one, rectangular merging (RM), starts from a set of rectangular fractures and merges them optimally to form L-shape fracturing. The second algorithm, direct L-shape fracturing (DLF), directly and effectively fractures the input layouts into L-shapes with sliver minimization. The experimental results show that our algorithms are very effective.

As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), manufacturability challenges are exacerbated. The nanopatterning through the 193nm lithography is being pushed to its limit, through double/triple or more general multiple patterning, while non-conventional lithography technologies such as extreme ultra-violet (EUV), e-beam direct-write (EBDW), and so on, still have grand challenges to be solved for their adoption into IC volume production. This tutorial will provide an overview of key overarching issues in nanometer IC design for manufacturability (DFM) with these emerging lithography technologies, from modeling, mask synthesis, to physical design and beyond.

Self-aligned double patterning (SADP) is a promising manufacturing option for sub-22nm technology nodes. Studies have shown that SADP provides better overlay control than traditional litho-etch-litho-etch double patterning. However, the use of stitch is not allowed, which makes layout decomposition for SADP more difficult. It is necessary to find a new solution to handle pattern conflicts and consider SADP in earlier stages. In this paper, we propose a novel multi-layer SADP-aware detailed routing with prescribed layout planning. Our method is based on a correct-by-construction approach to take SADP compliancy into account during routing, and to achieve layout decomposition simultaneously. The experimental result shows that the proposed approach consistently achieves SADP-compliant solutions on both single-layer and multi-layer designs.