44 results on '"Jhamb, Mansi"'
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2. A Novel Active Inductor Based Low Noise Amplifier for Analog Front End of Bio-medical Applications
3. Adder based digital control block for analog front end in biomedical applications
4. Aruco Marker-Based Pick and Place Approach Using a UR5 Robotic Arm and Vacuum Gripper
5. Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell
6. Low-Power LNA in Analog Front End for Biomedical Applications
7. Aruco Marker-Based Pick and Place Approach Using a UR5 Robotic Arm and Vacuum Gripper
8. Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application
9. Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell
10. Design of a low-power 180 nm broadband CMOS transimpedance amplifier for bio-medical & IoT applications
11. Efficient Fir Filter Based on Improved Booth Multiplier and Spanning Tree Adder
12. Challenges in VLSI Design for Efficient Energy Harvesting
13. Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate
14. Partial product based improved reconfigurable FIR filter with control logic for automated guided vehicles on virtex-7 FPGA
15. A Novel Design of Voltage and Temperature Resilient 9-T Domino Logic XOR /XNOR Cell
16. Efficient Fir Filter Based on Improved Booth Multiplier and Spanning Tree Adder
17. A 0.7 V 0.144 µW Frequency Divider Design with CNTFET-Based Master Slave D-Flip Flop
18. High-Performance Current Mirror-Based Voltage-Controlled Oscillator for Implantable Devices
19. Action Plan for a Two Wheeled Mobile Robot Navigation with Controlled Velocity Approach on MATLAB
20. Ultra Low Power Compressor Based Multiplier Circuits for Robots
21. Improved RSA with Enhanced Security on STM32 @ 84MHz.
22. Low Power and Highly Reliable 8-Bit Carry Select Adder
23. Ultra low power current mirror design with enhanced bandwidth
24. A 0.7 V 0.144 µW Frequency Divider Design with CNTFET-Based Master Slave D-Flip Flop
25. Performance Analysis of Comparator for IoT Applications
26. Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques
27. Power Optimization for Arithmetic Components in Assistive Digital Devices
28. Efficient adders for assistive devices
29. Design, implementation and performance comparison of multiplier topologies in power-delay space
30. Performance Analysis of Comparator for IoT Applications
31. A 0.8-Volt 29.52-μW Current Mirror-Based OTA Design for Biomedical Applications.
32. Aruco Marker-Based Pick and Place Approach Using a Ur5 Robotic Arm and Vacuum Gripper
33. Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate
34. Ultra low power design of multi-valued logic circuit for binary interfaces
35. A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design
36. Pipelined adders for ultralow-power wearables
37. Optimal contract pricing of load aggregators for direct load control in smart distribution systems
38. A high level implementation and performance evaluation of level-I asynchronous cache on FPGA
39. The Comparative Analysis of Low Power, High Speed Asynchronous Static Random Access Memory Architecture
40. Pulse Coded Modulation: A Novel Implementation for Enhanced Signal-to-Quantization Noise Ratio
41. Design and Performance Analysis of Latch Based C-Element in 90 nm Technology Regime and Beyond
42. A High Performance Real-Time Pulse Coded Modulation System Using Handshaking
43. A Novel Design of Efficient Delta Modulation System Using Four Phase Handshaking
44. Iris based human recognition system
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