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423 results on '"Jesshope, Chris"'

1. MGSim - Simulation tools for multi-core processor architectures

Author

Lankamp, Mike, Poss, Raphael, Yang, Qiang, Fu, Jian, Uddin, Irfan, and Jesshope, Chris R.

Subjects
Computer Science - Hardware Architecture, Computer Science - Distributed, Parallel, and Cluster Computing
Abstract

MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks., Comment: 33 pages, 22 figures, 4 listings, 2 tables

Published
2013

2. Application of Mobile Agents in Web-Based Learning Environment.

Author

Hong Hong, Kinshuk, He, Xiaoqin, Patel, Ashok, and Jesshope, Chris

Abstract

Web-based learning environments are strongly driven by the information revolution and the Internet, but they have a number of common deficiencies, such as slow access, no adaptivity to the individual student, limitation by bandwidth, and more. This paper outlines the benefits of mobile agents technology, and describes its application in Web-based learning environments to improve the learning process. The TILE (Technology Integrated Learning Environment) project aims to provide an integrated system for the management, authoring, delivery, and monitoring of education at a distance. Mobile agents technology is being used in the implementation of the TILE adaptation mechanism. (Author/AEF)

Published
2001

3. Teaching Cognitively Complex Concepts: Content Representation for AudioGraph Lectures.

Author

Heinrich, Eva, Jesshope, Chris, and Walker, Nic

Abstract

This paper investigates a solution to support the learning of cognitively complex concepts, through the recording, annotation and online delivery of multimedia lessons. Recording lessons for online delivery has the advantage of utilizing all of the pedagogical skills of the lecturers and teachers involved. To facilitate the retrieval of appropriate teaching material, the lessons are annotated using a notation called the Flexible Structured Coding Language (FSCL), which facilitates a rich and precise description of these concepts, in a natural language-like format. Different streams of meta data are produced to describe the lesson's properties, like cognitive type and media type. The approach to support the technology-based learning of cognitively complex concepts is based on the following elements: record complete lessons using the AudioGraph tools; capture different streams of meta data and associate those both with and within the media elements; and describe the lesson content using the FSCL. The approaches presented are set on the context of the IEEE draft standard on Learning Object Meta Data (LOM). (Contains 17 references.) (Author/AEF)

Published
2001

4. μTC – An Intermediate Language for Programming Chip Multiprocessors

Author

Jesshope, Chris, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Jesshope, Chris, editor, and Egan, Colin, editor

Published
2006
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5. Resource-Agnostic Programming for Many-Core Microgrids

Author

Bernard, Thomas A. M., Grelck, Clemens, Hicks, Michael A., Jesshope, Chris R., Poss, Raphael, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Guarracino, Mario R., editor, Vivien, Frédéric, editor, Träff, Jesper Larsson, editor, Cannatoro, Mario, editor, Danelutto, Marco, editor, Hast, Anders, editor, Perla, Francesca, editor, Knüpfer, Andreas, editor, Di Martino, Beniamino, editor, and Alexander, Michael, editor

Published
2011
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6. AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies

Author

Gamrat, Christian, Philippe, Jean-Marc, Jesshope, Chris, Shafarenko, Alex, Bisdounis, Labros, Bondi, Umberto, Ferrante, Alberto, Cabestany, Joan, Hübner, Michael, Pärsinnen, Juha, Kadlec, Jiri, Danek, Martin, Tain, Benoit, Eisenbach, Susan, Auguin, Michel, Diguet, Jean-Philippe, Lenormand, Eric, Roux, Jean-Luc, Cardoso, João M. P., editor, and Hübner, Michael, editor

Published
2011
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7. HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?

Author

Forsell, Martti, Hofstee, Peter, Jerraya, Ahmed, Jesshope, Chris, Vishkin, Uzi, Träff, Jesper Larsson, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Lin, Hai-Xiang, editor, Alexander, Michael, editor, Forsell, Martti, editor, Knüpfer, Andreas, editor, Prodan, Radu, editor, Sousa, Leonel, editor, and Streit, Achim, editor

Published
2010
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9. Evaluating CMPs and Their Memory Architecture

Author

Jesshope, Chris, Lankamp, Mike, Zhang, Li, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Berekovic, Mladen, editor, Müller-Schloer, Christian, editor, Hochberger, Christian, editor, and Wong, Stephan, editor

Published
2009
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10. An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency

Author

Jesshope, Chris, Philippe, Jean-Marc, van Tol, Michiel, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bereković, Mladen, editor, Dimopoulos, Nikitas, editor, and Wong, Stephan, editor

Published
2008
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11. The Verification of the On-Chip COMA Cache Coherence Protocol

Author

Vu, Thuy Duong, Zhang, Li, Jesshope, Chris, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Meseguer, José, editor, and Roşu, Grigore, editor

Published
2008
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12. On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores

Author

Zhang, Li, Jesshope, Chris, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bougé, Luc, editor, Forsell, Martti, editor, Träff, Jesper Larsson, editor, Streit, Achim, editor, Ziegler, Wolfgang, editor, Alexander, Michael, editor, and Childs, Stephen, editor

Published
2008
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13. Strategies for Compiling μTC to Novel Chip Multiprocessors

Author

Bernard, Thomas A. M., Jesshope, Chris R., Knijnenburg, Peter M. W., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Vassiliadis, Stamatis, editor, Bereković, Mladen, editor, and Hämäläinen, Timo D., editor

Published
2007
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14. Formalizing SANE Virtual Processor in Thread Algebra

Author

Vu, Thuy Duong, Jesshope, Chris, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Butler, Michael, editor, Hinchey, Michael G., editor, and Larrondo-Petrie, María M., editor

Published
2007
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16. Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors

Author

Hasasneh, Nabil, Bell, Ian, Jesshope, Chris, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Dough, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Grass, Werner, editor, Sick, Bernhard, editor, and Waldschmidt, Klaus, editor

Published
2006
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17. The Challenges of Massive On-Chip Concurrency

Author

Bousias, Kostas, Jesshope, Chris, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Srikanthan, Thambipillai, editor, Xue, Jingling, editor, and Chang, Chip-Hong, editor

Published
2005
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18. Scalable Instruction-Level Parallelism

Author

Jesshope, Chris, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Pimentel, Andy D., editor, and Vassiliadis, Stamatis, editor

Published
2004
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23. Building a Concurrency and Resource Allocation Model into a Processor’s ISA

Author

Jesshope, Chris, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, César, Eduardo, editor, Alexander, Michael, editor, Streit, Achim, editor, Träff, Jesper Larsson, editor, Cérin, Christophe, editor, Knüpfer, Andreas, editor, Kranzlmüller, Dieter, editor, and Jha, Shantenu, editor

Published
2009
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27. Asynchronous arbiter for micro-threaded chip multiprocessors

Author

Hasasneh, Nabil, Bell, Ian, and Jesshope, Chris

Abstract

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2006.10.004 Byline: Nabil Hasasneh (a), Ian Bell (b), Chris Jesshope (a) Abstract: This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token to the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring's timing. The arbiter provides a very simple arbitration mechanism and can be used for chip multiprocessor arbitration purposes. Author Affiliation: (a) Department of Computer Science, University of Amsterdam, Kruislaan 403, 1098 SJ Amsterdam, The Netherlands (b) Department of Electronic Engineering, University of Hull, HU6 7RX Hull, UK Article History: Received 6 October 2006; Accepted 9 October 2006

Published
2007

34. Introduction to Programming Multicores

Author

Jesshope, Chris, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bereković, Mladen, editor, Dimopoulos, Nikitas, editor, and Wong, Stephan, editor

Published
2008
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42. Programming with active data

Author

Jesshope, Chris, Miller, Philip, Yantchev, Jelio, Goos, G., editor, Hartmanis, J., editor, Barstow, D., editor, Brauer, W., editor, Brinch Hansen, P., editor, Gries, D., editor, Luckham, D., editor, Moler, C., editor, Pnueli, A., editor, Seegmüller, G., editor, Stoer, J., editor, Wirth, N., editor, Wolf, Gottfried, editor, Legendi, Tamáas, editor, and Schendel, Udo, editor

Published
1989
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44. Trends in Web-based Learning Environments.

Author

Hong, Hong, Kinshuk, He, Xiaoqin, Patel, Ashok, and Jesshope, Chris

Abstract

Discusses trends in Web-based learning environments. Highlights include common features of existing Web-based learning environments; challenges; the large amount of available online educational material; adaptation and dynamic interaction; real-time interaction; and monitoring online testing. (LRW)

Published
2001

45. Architectural approach to the role of optics in monoprocessor and multiprocessor machines

Author

Collet, Jacques Henri, Litaize, Daniel, Van Campenhout, Jan, Jesshope, Chris, Desmulliez, Marc, Thienpont, Hugo, Goodman, James, and Louri, Ahmed

Subjects
Multiprocessors -- Design and construction, Optics -- Equipment and supplies, Computers -- Optical equipment, Architecture -- Usage, Astronomy, Physics
Abstract

The relevance of introducing optical interconnects (OI's) in monoprocessors and multiprocessors is studied from an architectural point of view. We show that perhaps the major explanation for why optical technologies have nearly been unable to penetrate into computers is that OI's generally do not shorten the memory-access time, which is the most critical issue for today's stored-program machines. In monoprocessors the memory-access time is dominated by the electronic latency of the memory itself. Thus implementing OI's inside the memory hierarchy without changing the memory architecture cannot dramatically improve the global performance. In strongly coupled multiprocessors the node-bypass latency dominates. Therefore the higher the connectivity (possibly with optics), the shorter the path to another node, but the more expensive the network and the more complex the structure of electronic nodes. This relation leaves the choice of the best network open in terms of simplicity and latency reduction. The bottlenecks resulting from and the benefits of implementing OI's are discussed with respect to symmetric multiprocessors, rings, and distributed shared-memory supercomputers. [C] 2000 Optical Society of America OCIS codes: 200.4650, 200.2610.

Published
2000

46. HPPC 2009 Panel:Are Many-Core Computer Vendors on Track?

Author

Forsell, Martti, Hofstee, Peter, Jerraya, Ahmed, Jesshope, Chris, Vishkin, Uzi, Larsson Träff, Jesper, Lin, Hai-Xiang, Alexander, Michael, Forsell, Martti, Knüpfter, Andreas, Prodan, Radu, Sousa, Leonel, and Streit, Achim

Subjects
ComputingMilieux_MISCELLANEOUS
Abstract

The last session of the HPPC 2009 workshop was dedicated to a panel discussion between the invited speakers and three additional, selected panelists. The theme of the panel was originally suggested by Uzi Vishkin, and developed with the moderator. A preamble was given in advance to the five panelists, and provoked an intensive and determined discussion. The panelists were given the chance to briefly summarize their view- and standpoints after the panel.

Published
2010

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