554 results on '"Janusz Rajski"'
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2. Generation of Two-Cycle Tests for Structurally Similar Circuits.
3. H2B: Crypto Hash Functions Based on Hybrid Ring Generators.
4. Hybrid Ring Generators for In-System Test Applications.
5. A Lightweight True Random Number Generator for Root of Trust Applications.
6. X-Masking for Deterministic In-System Tests.
7. A New Static Compaction of Deterministic Test Sets.
8. X-Masking for In-System Deterministic Test.
9. Hardware Root of Trust for SSN-basedDFT Ecosystems.
10. Test Generation for an Iterative Design Flow with RTL Changes.
11. DIST: Deterministic In-System Test with X-masking.
12. Fast Test Generation for Structurally Similar Circuits.
13. Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations.
14. LBIST for Automotive ICs With Enhanced Test Generation.
15. Efficient Test Compression Configuration Selection.
16. Convolutional Compaction-Based MRAM Fault Diagnosis.
17. On Reduction of Deterministic Test Pattern Sets.
18. Test Sequence-Optimized BIST for Automotive Applications.
19. Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.
20. Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
21. Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs.
22. X-Tolerant Tunable Compactor for In-System Test.
23. Effective Design of Layout-Friendly EDT Decompressor.
24. Defect-Oriented Test: Effectiveness in High Volume Manufacturing.
25. Autonomous Scan Patterns for Laser Voltage Imaging.
26. X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan.
27. Time and Area Optimized Testing of Automotive ICs.
28. Test Time and Area Optimized BrST Scheme for Automotive ICs.
29. On Cyclic Scan Integrity Tests for EDT-based Compression.
30. Scan Integrity Tests for EDT Compression.
31. Low Cost Hypercompression of Test Data.
32. Deterministic Stellar BIST for Automotive ICs.
33. DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies.
34. On New Class of Test Points and Their Applications.
35. Deterministic Stellar BIST for In-System Automotive Test.
36. Hypercompression of Test Patterns.
37. Staggered ATPG with capture-per-cycle observation test points.
38. Logic BIST With Capture-Per-Clock Hybrid Test Points.
39. ROM fault diagnosis for O(n2) test algorithms.
40. Full-scan LBIST with capture-per-cycle hybrid test points.
41. Efficient Prognostication of Pattern Count with Different Input Compression Ratios.
42. Hardware Protection via Logic Locking Test Points.
43. Transistor stuck-on fault detection tests for digital CMOS circuits.
44. Minimal area test points for deterministic patterns.
45. Test point insertion in hybrid test compression/LBIST architectures.
46. On Test Points Enhancing Hardware Security.
47. Efficient Test Compression Configuration Selection
48. Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.
49. Trimodal Scan-Based Test Paradigm.
50. Embedded Deterministic Test Points.
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