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This paper presents a reliable nonvolatile static gain cell made of two transistors and two magneto-tunneling junctions (MTJs) for cache memory application. The wide distribution in the resistance of MTJs in parallel and anti-parallel states and the variations in the threshold voltage of gain cells are overcome by connecting two complementary MTJs and self-reference sensing circuits, respectively. An enhanced sensing margin and immunity to read disturbance are achieved by applying high voltage across the stacked complementary MTJs. The sensing margin of $8\sigma $ is assured after the Monte Carlo simulation using the measured parameters of the MTJ, including a tunneling magneto-resistance of 200%, a 5% distribution of resistance, and a 5% distribution of threshold voltage in the 65 nm standard CMOS process.

This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.

A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to reduce self refresh current with minimum chip size burden. Stacking of 2 dies with 7.5 μm diameter and 40 μm pitch TSVs has been fabricated and tested, which results in 76% overall package yield without difference in performances between top and bottom die.

In this paper, a symmetric dual-gate single-Si TFT, which is composed of three split floating n+ zones, is simulated. This structure remarkably reduces the kink-effect and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by the floating n+ region. This structure allows effective reduction in the kink-effect, depending on the length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate. This result demonstrates 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction in output conductance in the saturation region, is observed. In addition, the reduction of hole concentration in the channel region, in order to effectively reduce the kink-effect, is confirmed.

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAM's, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.

In this Paper, we present a design of source driver driving a current driven AMOLED Panel. Generally, a current driven AMOLED pixel has a long programming time in low current level. But, the proposed source driver reduces a programming time with employing a voltage DAC for pre-charging. It will make possible to use the large scale display panel on mobile applications even stationary applications.

Infrared bolometer sensor's variation is detected by voltage drop between a reference resistor and a bolometer resistor in this architecture. One of the serious problems in this architecture is that these resistors value has a process variation. So common-mode level could be different from expectation value in room temperature. Different common-mode level could lead to wrong output at the end of readout circuit. We suggest useful method to solve this problem. Difference correction using capacitor has reduced CM level difference to 88.5 % for I MΩ bolometer and reference resistor's 10 % variation.