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This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels–coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub- $V_{\mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort.

This chapter presents the mixed -signal design approach for the design of neuromorphic platforms for the biomedical signal processing. The proposed approach combines algorithmic, architectural and circuit design concepts to offer a low -power neuromorphic platform for streaming biomedical signal processing. The platform employs liquid state machines using spiking neurons (implemented on analog neuron circuits) and support vector machine (SVM) (implemented as software running on advanced RISC machine (ARM) processor). A dynamic global synaptic communication network realized using the ultralow leakage IGZO thin film transistor (TFT) technology circuit switch is also presented. The proposed architectural technique offers a scalable low -power neuromorphic platform design approach suitable for processing real-time biomedical signals.

In this paper a capacitive coupled radio-frequency identification tag fabricated on flexible thin-film substrate is presented. The antenna of the tag is monolithic integrated “on-chip”. The footprint of the tag is defined by the size of the antenna, 1cm2. The tag operated at 24V applied reader voltage at a frequency of 1MHz. The achieved data transmission speed of the thin-film tag is 5.8kbps. The technology is a unipolar indium gallium zinc oxide (IGZO) self-aligned transistor architecture.

This chapter focuses on a review of state-ofthe- art memory designs and new design methods for near-threshold computing (NTC). In particular, it provides a survey of existing low voltage memory techniques and their pros and cons. It also presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is validated by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vt voltage level as the digital logic. Reliability degradation is thus Overcome, which opens the path to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to a view of the future evolution towards 14, 10 and 7 nm technology nodes.

In order to provide better services to elderly people, home healthcare monitoring systems have been increasingly deployed. Typically, these systems are based on wireless sensor nodes, and should utilize very low energy during their lifetimes, as they are powered by scavengers. In this article, we present an ultra-low power processing system for a wireless sensor node for very low duty cycle applications. In the CoolBio system-on-chip, we utilized several power reduction techniques at both the architecture level and the circuit level. These techniques include feature extraction, voltage and frequency scaling, clock and power gating and a redesign of key standard cells. In the design of the ultra-low power processing system, we paid special attention to the memory subsystem, as it is one of the most power-consuming modules in a design. We also designed a clock manager in order to reduce the power consumed by clocking, and a power manager that is able to power-off unutilized modules. The proposed wireless sensor node processing system consumes 36.4μW at 100MHz and 1.2V supply voltage, for a heartbeat-detection algorithm with a 0.01% duty cycle.

This paper presents a novel low-to-high level shifter that enables having voltage domains with substantially different supply voltages from near-threshold to full supply voltage. The level shifter was designed in a 90nm CMOS technology and uses thick-oxide transistors, non-minimum channel length transistors, along with novel circuit structures to up convert from 0.36V to 1.32V and all the voltage levels in between for all process corners and the temperature range of [0°C – 125°C]. Relaxing the temperature operating range to [25°C – 125°C], the level shifter works deep into the sub threshold region capable of up converting from 0.31V to 1.32 V. For the typical case operating condition, the proposed level shifter has an unprecedented performance of 1.5 ns while up converting 0.36V to 1.32V.

Energy efficient computation becomes increasingly important for battery driven ubiquitous computing applications. To extend the battery life time while still meeting the performance demands, the designers face critical challenges in choosing the appropriate circuit topologies and low-power design techniques in order to optimally balance the power and performance trade-offs. In this paper, we evaluate various form of single-ended body bias configuration and experimented the fine-grained self-adaptive circuit optimization technique such as pull-up body bias and pull-down body bias to combine the monotonic precharge-evaluate logic circuits and application of body bias based on the evaluation and idle modes within logic stages. This technique improves the evaluation delay by 19% and 16% with 15% and 10% lower energy consumption for the non-clocked and clocked 16-bit CLA adder respectively.

The antenna of the tag is monolithic integrated ”onchip”. The footprint of the tag is defined by the size of the antenna, 1cm2. The tag operated at 24V applied reader voltageat a frequency of 1MHz. The achieved data transmission speed of the thin-film tag is 5.8kbps. The technology is a unipolar indium gallium zinc oxide (IGZO) self-aligned transistor architectur.

This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.

The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without clock architecture, with co-located memory and processing capability that exploits event-based processing to reduce an always-on system's overall energy consumption (μW dynamic operation). The chip area in a 40 nm Complementary Metal Oxide Semiconductor (CMOS) digital technology is 2.82 mm2 including pads (without pads 1.42 mm2). This small area footprint enables μBrain integration in re-trainable sensor ICs to perform various signal processing tasks, such as data preprocessing, dimensionality reduction, feature selection, and application-specific inference. We present an instantiation of the μBrain architecture in a 40 nm CMOS digital chip and demonstrate its efficiency in a radar-based gesture classification with a power consumption of 70 μW and energy consumption of 340 nJ per classification. As a digital architecture, μBrain is fully synthesizable and lends to a fast development-to-deployment cycle in Application-Specific Integrated Circuits (ASIC). To the best of our knowledge, μBrain is the first tiny-scale digital, spike-based, fully parallel, non-Von-Neumann architecture (without schedules, clocks, nor state machines). For these reasons, μBrain is ultra-low-power and offers software-to-hardware fidelity. μBrain enables always-on neuromorphic computing in IoT sensor nodes that require running on battery power for years.

In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit. We propose a mixed-radix encoding system for a multi-device synaptic unit achieving high classification accuracy (94%) including device variability. To our knowledge, this is the first paper to discuss the tradeoff between single and multi-device synaptic weight in terms of design and technology using silicon data. We have demonstrated that high level of variability can be handled by the neuromorphic algorithm. The results presented in the paper has been obtained from 1Mb array.