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We systematically investigated the wafer- bonded interfaces of p+GaAs/n+InGaAs and p+InGaAs/ n+InGaAs by using a circular transmission line method (CTLM) for the increased extraction accuracy. Based on the low-temperature bonding process at 50 °C, the bonded interfaces were successfully fabricated without degradation of the material quality. While the fabricated devices exhibited the linearly increased resistance as a function of channel distances, the p+InGaAs/n+InGaAs structure revealed the improved interfacial resistivity of $3.9\times 10^{-3} \,\, \Omega \cdot \text{cm}^{2}$ compared with $3.3\!\times \!10^{-2} \,\, \Omega \cdot \text{cm}^{2}$ of the p+GaAs/n+InGaAs. Since these values suggested good electrical properties in wafer-bonded structures, the developed wafer-bonded interfaces could be a good approach for integrating electronic and optoelectronic devices.

In this article, we have demonstrated 125-nm-gate InGaAs-on-insulator (InGaAs-OI) high-electron-mobility transistors (HEMTs) on Si substrates via wafer bonding. The highlights of this device were the i-In0.53Ga0.47As/i-InAs/i-In0.53Ga0.47As quantum-well channel for high RF performance by improving electron transport properties and the low processing temperature of 250 °C or less for monolithic 3-D integration. As a result, we obtained a current gain cutoff frequency ( ${f}_{\text {T}}$ ) of 227 GHz and a maximum oscillation frequency ( ${f}_{\text {MAX}}$ ) of 187 GHz. These results are the highest ever reported in monolithic 3-D RF transistors above ${L}_{\text {G}} = {100}$ nm. In addition, through the small-signal modeling, we have found that the impact of the back-gate (BG) on RF performances of top devices is a critical issue in M3D RF systems.

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

A recursive filtering technique is developed to improve the computational efficiency of explicit-filter large-eddy simulation in highly parallelized computational environments. In parallel computations on a partitioned domain, unlike in non-recursive explicit filtering in which the number of ghost cell layers for storing neighbor cell values to ensure communication with neighbor partitions is increased rapidly as the stencil of the filter becomes wider, the present recursive filtering technique requires only a single layer of ghost cells for storing immediate neighbor cell values regardless of the stencil width of the filter. A generalized algorithm for construction of recursive filters with desired filter widths is developed. The computational efficiency of the proposed recursive filtering technique over the conventional non-recursive broad-band filtering techniques in terms of memory usage and computational time is presented.

A new numerical method to solve three-dimensional wave equations in media with arbitrarily-shaped interfaces on a Cartesian grid is proposed. The present method aims to achieve two objectives to simulate wave propagation through realistic geometries: (1) handling wave interaction at the interface with high ratios of acoustic material properties and (2) treating complex geometries involving both smooth and non-smooth interfaces. To achieve the first objective, the present method extends the solution smoothly across the interface in the direction normal to the interface. A cell layer of ghost points on each side of the interface is used to enforce interface conditions, which support not only reflection but also transmission of incident waves. Ghost-point values are determined by applying a local coordinate-transform and a weighted least squares error method, which suppress numerical instabilities. To achieve the second objective, the interface geometry is approximated using an unstructured surface mesh, which does not require analytic information about the interface geometry. Finally, the accuracy and effectiveness of the present method are validated and demonstrated for wave propagation over or through several two-dimensional and three-dimensional obstacles.

BACKGROUND A complete release of the transverse nasalis aponeurotic fibers (TNAFs) during Asian rhinoplasty is critical for accurate positioning of the nasal implant and lengthening of the short nose. The objectives of this article are to clarify the anatomy of the TNAFs using cadaveric dissections and to present the clinical results after complete TNAF release in Asian rhinoplasty. METHODS An anatomical dissection was performed in 8 cadavers to study the TNAFs, specifically the origin, insertion, and boundary of the TNAFs and the effect of the TNAF release on nasal length. Between January 2012 and December 2014, 2314 open implant augmentation rhinoplasties (1777 primary and 537 secondary) were performed by the senior author (J.J.). The records of these patients were retrospectively reviewed for results of TNAF release. A separately designed prospective clinical study was performed to document the nasal envelope extension after TNAF release in 52 consecutive patients. RESULTS In the cadaver study, the anatomy and the boundaries of the TNAFs were clearly visualized and documented. With accurate release of the TNAFs, the ideal pocket for nasal implant can be defined, and the effect of the release of the TNAFs recorded. Release of the TNAFs also allows extension of the nasal envelope. However, measurements of the nasal envelope were not studied in the cadaver because the skin was degloved.From the clinical study with a follow-up ranging from 6 months to 1.5 years, the overall complication of open rhinoplasty using silicone implants incorporating TNAF release was 6%. In this group, 3.4% of patients required revision rhinoplasty. Releasing the TNAFs ensures an accurate implant pocket reducing the risk of implant deviation and implant visibility and increases the nasal length by 2.1 mm. CONCLUSIONS Complete release of the TNAFs is especially important in Asian rhinoplasty to facilitate accurate pocket dissection, allowing the extension of the nasal envelope in order to correct short nose or secondary contracted nose.

This research aims at investigating the user requirements at the service level for safe navigation system, following e-navigation strategy implementation plan. The user requirements is surveyed to collect real-time navigational information and then to find out services through the presentation of the collected information. To provide the information on user needs for the system developer, a questionnaire survey has been made. Based on this surveys, this research investigated which navigational information is with higher priority for the safe navigation during ship operation by bridge team in harbour and in coastal and confined.

To electrically characterize ball grid array (BGA) packages, one-port S -parameter measurements have been performed. Equivalent circuit parameters using the Γ and T models are extracted from measured S -parameters for three different frequency ranges. The accuracy of two selected equivalent circuits is evaluated by comparison between the re-calculated S 11 using the extracted equivalent circuit parameters and measured S -parameters. The results show that the T lumped model can be used to represent S -parameters of BGA packages without distributed elements up to 2 GHz.

Ball grid array (BGA) packages have been characterized from one port S-parameter measurements by shorting and opening the connection on the ball side of BGA packages. Transmission line parameters (resistance, inductance and capacitance) using the /spl Gamma/ equivalent circuit model are extracted from the measured S/sub 11/ parameter. Extracted resistances are strongly dependent on frequency, but extracted inductances and capacitances are nearly constant up to 500 MHz. Extracted capacitances are well matched to those measured from an LCR meter and calculated from a three-dimensional (3-D) simulator, Capacitance in a transmission line plays an important role in electrical performance for packages so that we may model a transmission line as a single capacitor. Extracted capacitances using the single capacitor model also well represent the measured S/sub 11/. These results suggest that the single capacitor model can be efficiently used for the transmission line model in BGA packages up to 500 MHz.

We report electrical characterization of ball grid array (BGA) packages solely from 1-port S-parameter measurements below 500 MHz. The capacitance, inductance and resistance of transmission lines in the packages are extracted. Extracted capacitances are compared with those from simulations and measurements at low frequency.