Search

In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics.

A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.

We present a Monte Carlo simulation and modelling method for single-electron nanocrystal memories including the nanocrystal inter-dot effect. A nanocrystal memory is modelled as a network of modified single-tunnel junctions for its programme operation and as a network of channel resistances for simulating drain current to extract its threshold voltage. Additionally, in each modelling, capacitive coupling between each geometrical element was determined using a device simulator. The results show that nanocrystal memory parameters are closely related to both static and dynamic programming characteristics, especially in the single-charging property. When the inter-dot spacing is large, a step-like single-charging feature becomes salient, but the threshold voltage shift between each state decreases. In contrast, when the dots are spatially closer, the threshold voltage shift between each state increases, while the step-like shape vanishes and resembles that of conventional flash memories. From the dynamic viewpoint, a closer spacing of dots makes it easier to charge the nanocrystal memory quantum dots more uniformly. The presented method will be helpful for the design of single-electron nanocrystal memories.

We report theoretical results for the distortions of electric equi-potential (EEP) planes in a liquid crystal (LC) film in the presence of surface geometrical grating (SGG). A scaled parameter, the ratio of capacitance per unit area of a LC to that of SGG, is introduced into a simple model to predict the distortions of EEP planes. It is found that the distortions of EEP planes are enhanced by increasing the spatial variations of this scaled parameter inside LC cell. These spatial variations naturally induce the spatially periodic deformations of the LC director which can be employed as a voltage-controlled optical grating.

The room temperature-operation of a single-electron metal-oxide-semiconductor (MOS) memory with a defined quantum dot fabricated by sidewall patterning technique based on conventional VLSI technologies has been demonstrated without the aid of electron beam (EB) lithography for the first time. Sidewall patterning technique shows a good uniformity and controllability as well as high throughput. The fabricated memory devices show quantized threshold voltage shifts at room temperature. Time-dependant measurement of drain current shows discrete electron injection to the quantum dot. In addition, fabricated devices have good subthreshold swing and retention characteristics.

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0/spl times/10/sup 14//cm/sup 2/ and 2.0/spl times/10/sup 14//cm/sup 2/. Initial O/sub 2/ injection method was applied for gate oxidation. The method is composed of an O/sub 2/ injection/N/sub 2/ anneal/main oxidation, and the control process is composed of a N/sub 2/ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 /spl mu/m have been fabricated by use of the method. Compared to the control process, the initial O/sub 2/ injection process increases the amount of nitrogen piled up at the Si/SiO/sub 2/ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved.

We investigated the charge decay characteristics of a silicon-oxide-nitride-oxide-silicon type nonvolatile memory at elevated temperatures. Based on the amphoteric trap model and the thermal emission model of the trapped charge, we propose an advanced charge decay model which includes the effect of the bottom oxide, and apply it to extraction of the trap density distribution in energy levels of the nitride layer. The samples prepared have nitride films deposited simultaneously and are classified into two groups according to the thickness of the bottom oxide. The trap density distributions extracted from two groups showed good consistency.

Vertical NAND (VNAND) technology relies on polysilicon for channel material. Two intrinsic variation sources of the cell threshold voltage induced by polysilicon traps have been identified and simulated: Random Trap Fluctuation (RTF) and Random Telegraph Noise (RTN). We demonstrate that RTN is enhanced by the polysilicon material and an original model explains the asymmetric RTN distribution observed after endurance. This work enables the prediction of V T distribution for VNAND devices in MLC operation.

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F2. Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.

We report on the self-formation of microdomains by the topographical and fringe field effects in a twisted nematic liquid crystal display (LCD) with dielectric surface gratings (DSG). A regular array of the DSG produces periodically aligned microdomains in each pixel because of the topographical alignment of the LC and the spatial variations of the effective voltage across the LC layer. The mutual optical compensation within each pixel is naturally achieved and thus the range of viewing in the LCD is significantly extended without complex surface treatments.

We measured instant VΛ change coming from the relaxation effect in high-k dielectric layer in CTF. A counter-pulse scheme was proposed to solve the issue in CTF memory, by inserting short positive gate pulse between erase execution pulse and verify read step, whose validity was confirmed in our NAND test vehicle main cell array.

We propose and implement a promising fabrication technology for geometrically well-defined single-electron transistors based on a silicon-on-insulator quantum wire and side-wall depletion gates. The 30-nm-wide silicon quantum wire is defined by a combination of conventional photolithography and process technology, called a side-wall patterning method, and depletion gates for two tunnel junctions are formed by the doped polycrystalline silicon sidewall. The good uniformity of the wire suppresses unexpected potential barriers. The fabricated device shows clear single-electron tunneling phenomena by an electrostatically defined single island at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions.

Charge trap flash (CTF) memory is one of the most promising technologies for the next generation NAND technology. Among various CTF memories, excellent manufacturability of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) structure has been successfully developed by achieving 32Gb MLC NAND flash using 40nm technology node (Y. Park et al., 2006). 3 dimensional NAND cells such as hemispherical corner (HC) (D. Kwak et al., 2007) and FinFET TANOS (S. Lee et al., 2006) devices with suppressed short-channel effects and improved data retention characteristic were also proposed as cell structures for the next generation beyond 40nm technology node. However, understanding of other device characteristics such as disturb characteristics of the structures is still insufficient. In this paper, various device characteristics of rounded corner (RC) TANOS including disturb and data retention characteristics are investigated and compared with the conventional planar TANOS. Finally, the rendering of RC TANOS for improving disturb characteristics was proposed.

In the proposed new scheme, which is named self aligned trap-shallow trench isolation (SAT-STI), such process damage on high-k layer can be minimized, achieving the goal of isolating the storage nitride layer successfully.

A p-channel SONOS memory, based on band-to-band tunneling initiated avalanche hot-hole injection mechanism, was firstly proposed to solve the F-N erase problem in NAND flash application. The fabricated device with 50-nm gate length effectively suppressed the short channel effect and featured an excellent program and erase performance, where the time scale of a few and /spl sim/100 /spl mu/sec could be obtained, respectively.

For the breakthrough of scaling limit, simple structure memories are developed and also multi-bit operation memories are introduced concurrently. A new TSM-ISP cell which has 30 nm local twin SONOS memory separated by the inverted sidewall patterning method under the 90 nm merged-triple gate. This new cell structure provides perfect 2-bit program, excellent endurance, erase characteristics and retention compared with the conventional single ONO type SONOS in the sub-90-nm regime.

A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of CMOS/SET hybrid logic. It is demonstrated that a universal literal gate with complementary self-biasing scheme operates quite well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation degrades severely.

In this paper, we propose a new experimental technique, namely the parallel stressing method to investigate the breakdown mechanism of MOS capacitors. The SILC characteristics of the region excluding the breakdown spot of a broken-down capacitor can be deduced, utilizing this method. It was shown that HBD as well as SBD takes place locally, as expected. Multiple SBD phenomena at different points on a capacitor have been verified. However, HBD has not occurred multiply, which is thought to be because of the decrease in stress intensity after the event.

We present a Monte Carlo simulation method for single-electron nanocrystal memories including the nanocrystal interdot effect, and show the simulation results obtained. A nanocrystal memory was modeled as a network of modified single-tunnel junctions for its program operation and as a network of channel resistances for simulating drain current to extract its threshold voltage. The results show that, in programming characteristics, device parameters have mutual trade-off relationships in the clearness of steplike single-charging features and in the magnitude of threshold voltage shifts. The presented method will be helpful for the design of single-electron nanocrystal memories.

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

We present a Monte Carlo simulation method for single-electron nanocrystal memories including the nanocrystal interdot effect, and show the simulation results obtained. A nanocrystal memory was modeled as a network of modified single-tunnel junctions for its program operation and as a network of channel resistances for simulating drain current to extract its threshold voltage. The results show that, in programming characteristics, device parameters have mutual trade-off relationships in the clearness of steplike single-charging features and in the magnitude of threshold voltage shifts. The presented method will be helpful for the design of single-electron nanocrystal memories.

Nitrogen implantation effect on SiO2/Si interface roughness is analyzed and a new method for growing ultrathin gate oxide is proposed. Interface roughness is improved by nitrogen implantation; the root-mean-square values measured by atomic force microscopy are 2.72–2.79 A, 1.7–2.12 A, and 2.12–2.33 A for 0, 1.0×1014/cm2, and 2.0×1014/cm2 nitrogen implantation, respectively. Initial O2 injection method is composed of O2 injection/N2 anneal/main oxidation, and the control process is composed of N2 anneal/main oxidation. The purpose of O2 injection is to form an extremely thin oxide layer that provides a Si/SiO2 interface at which nitrogen is accumulated during N2 annealing process. Time of flight secondary ion mass spectroscopy data show that the initial O2 injection method has a higher peak than that of the control process. The oxidation reduction rates of the control process were: 0.6% (15.4 A/15.5 A), 18.2%(26.9 A/32.9 A), and 16.4% (34.1 A/37.4 A) for the wafers of 1, 10, and 20 min oxidation time, resp...