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In this paper, we demonstrated experimentally a lateral GaN-based junction field effect transistor (JFET). A selective area regrowth of p-NiO on the as-grown n-GaN channel layer was developed by magnetron sputtering at room temperature to form the p–n junction. A self-aligned gate process and a post metal annealing process were employed to improve the device performances. The measured results show that the annealed JFET exhibits an ON/OFF ratio exceeding 106 and a higher breakdown voltage up to 814 V without any terminal structure. The breakdown voltage is determined by the reverse breakdown of parasitic PN junction between gate and drain. Further, the threshold voltage of the p-NiO/n-GaN JFET exhibits excellent temperature stability in the range of 300–500 K. [ABSTRACT FROM AUTHOR]

Two‐dimensional non‐layered tellurene (Te) can serve as a promising candidate in transistor applications because of its high carrier mobility and air stability. However, it is still quite challenging in aspect of ultra‐thin channel and gate‐control ability in conventional metal‐oxide‐semiconductor field‐effect transistor architecture. This work proposes a facile thinning strategy for solution‐proceed Te flakes and fabricates a junction field‐effect transistor (JFET) architecture, that has well addressed the above‐mentioned two issues. Through a mild oxidative thinning process, the post‐growth Te flakes are thinned from bulk to few‐layer, guaranteeing the highly efficient electrostatic doping as a transistor channel. Then, a four‐terminal JFET‐based on p‐Te and n‐ReS2 is designed, achieving a multifunctional integration of rectification diode, p‐ and n‐channel transistor in one single device. By accessing different contact scheme, the ReS2/Te p‐n diode is explored with a rectification ratio of 103, the p‐channel JFET exhibits a high hole mobility of 317.6 cm2V−1s−1, ideal low subthreshold swing of 84 mV dec−1. While the n‐channel JFET is obtained with electron mobility of 67.6 cm2 V−1s−1 and SS of 229 mV dec−1. Both p‐ and n‐channel devices showcase clear saturation characteristic with ultra‐small pinch‐off voltage (≈0.4 V), which is crucial for low‐power logical and integrated circuit applications. [ABSTRACT FROM AUTHOR]

The 1.7 kV 4H-SiC MOSFET which features optimized retrograded-profile ion implantation in the JFET regions (RG-MOS) is proposed and fabricated on the 4 inch wafers. The measured results quantify the benefits of the RG-MOS structure: simultaneous improvement in high-frequency figures of merit (HF-FOM) (R on× C GD) by 1.5×, HF-FOM (R on × Q GD) by 1.5× and Baliga figure of merit (BFOM = 4BV2/ R on,sp) by 1.6× compared with the conventional MOSFET (CON-MOS). Unlike other reported complicated structures which need high-precise fabricating process, the proposed RG-MOS structure is compatible with the prior planar 4H-SiC MOSFET process, and is favorable for large-scale production. [ABSTRACT FROM AUTHOR]

In this paper, we present a monolithically integrated temperature sensor for a 4H-SiC JFET. This uses a lateral resistor formed by the P+ gate implant. The sensor resistance is dependent on the number of ionized dopants, which increases with temperature. Drift-diffusion simulations considering device self-heating have been carried out, which show the JFET exhibits a breakdown voltage of 1480 V and a nominal threshold voltage (Vth) of −4.3 V. We show that the sensor has a high degree of linearity (R2) of 0.996 between 25–150∘C. Breakdown voltage of the JFET with the integrated sensor is found to reduce as the spacing (S) between the gate junction, the adjacent floating guard ring (FGR) and the sensor junction increases. However, it is found that a large variation in sensor current (ΔIsens) is experienced in the off-state if S is small. An optimum value of S = 0.95 µm was found to maintain 90% of the JFET breakdown voltage, whilst only exhibiting ΔIsens= 3.4%. The impact of contact resistance to the total sensor resistance is ≤1%. In addition, the sensor robustness during switch-off is good, due to the high doping in the P+ layer. The proposed sensor can be integrated into 4H-SiC JFET without any modification of existing process flows, or additional mask layers to provide real-time temperature monitoring with high accuracy.

An inertial sensor is a crucial payload in China's Taiji program for space gravitational wave detection. The performance of the capacitive displacement sensing circuit in the low-frequency band (0.1 mHz to 1 Hz) is extremely important because it directly determines the sensitivity of the space gravitational wave detection missions. Therefore, significant, yet challenging, tasks include decreasing the low-frequency noise in capacitive displacement sensing circuits and improving the capacitive sensing resolution. This study analyzes the noise characteristics of the pre-amplifier circuit within the capacitive sensing circuit, achieves precise tuning of the transformer bridge, and examines how transformer parameters affect noise. In addition, this study introduces a method using a discrete JFET to reduce the operational amplifier current noise and analyzes how feedback resistance and capacitance in TIA circuits affect the overall circuit noise. The proportional relationship between different transformer noises and TIA noise before and after optimization was analyzed and experimentally verified. Finally, an optimized TIA circuit and a superior transformer were utilized to achieve an increase in the capacitive sensing resolution from 1.095 aF/rtHz @ 10 mHz to 0.84 aF/rtHz @ 10 mHz, while improving the performance by 23%. These findings provide valuable insights into further decreasing circuit noise and increasing the capacitive sensing resolution. [ABSTRACT FROM AUTHOR]

As the demand for medium-voltage power semiconductors continues to rise, the super-cascode switch has emerged as a promising solution. This paper presents the design, implementation, and experimental evaluation of a 6.5 kV, 400 A super-cascode power module. This treatment includes an in-depth analysis of the theory of operation for this topology, as well as a set of design guidelines to facilitate the realization of practical implementations. To validate the functionality and performance of the realized prototype module, double-pulse test experiments were conducted under a wide range of operating conditions, deploying metrics specially targeted for the super-cascode switch. These experimental results demonstrate that adherence to the design guidelines provided in this paper yields a super-cascode switch with exceptional performance. In fact, the super-cascode module evaluated in this paper achieves switching performance on par with that of medium voltage SiC MOSFET modules, and far beyond that of medium voltage Si IGBT modules. Overall, this investigation contributes to the understanding of the factors driving the operation and performance of the super-cascode switch, especially under high current conditions.

The super-cascode switch (SCS) has gained significant attention in the last decade due to its ability to achieve medium-voltage ratings using low-voltage semiconductors. However, there exists a notable absence of quantitative metrics to effectively evaluate the performance of the SCS. This gap exists because the behavior of the SCS is different from that of a traditional semiconductor switch, and traditional semiconductor performance metrics are not adequate for its evaluation. The present manuscript addresses this gap by introducing new figures of merit that are designed to evaluate the unique characteristics of the SCS. The practical value of these metrics is also demonstrated through a set of experimental studies. By applying these new figures of merit to one of the best-performing SCS configurations described previously in the literature, several opportunities for improvement are revealed. The SCS prototype described in this paper is evaluated experimentally at bus voltage levels up to 3.5 kV and current levels up to 200 A, demonstrating substantial performance improvements relative to the baseline configuration from the literature. These improvements are the result of iterative refinements to the balancing network, which are selected through a process that is informed by the application of the proposed figures of merit.

In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown performance have been completed for different gate junction depths (xj) and mesa widths (MW). Due to the short channel length, realistic implant doping profiles extracted from experimentally calibrated Monte-Carlo based SRIM simulations have been used. Two suitable designs to eliminate premature DIBL-induced failure have been found: xj = 0.7 µm for MW=1.75 µm, and xj = 1 µm for MW=2 µm. We found that a 0.3 µm junction depth has a breakdown voltage of only 50 V due to collapse of the source-drain barrier at a relatively low drain bias. Threshold voltage (Vth) decreases with increasing junction depth, approaching 0 V. This is due to a combination of greater lateral straggling of implanted ions and improved electrostatic control of the channel. Our calculations demonstrate that the most robust option to mitigate DIBL and consequently early breakdown is to maintain xj ≥1 µm. At this depth, the threshold voltage has a weak dependence on drain bias, indicating diminishing SCEs. Decreasing the mesa width mitigates early breakdown but requires a mesa width of less than 1.75 µm, which poses fabrication challenges.

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This paper presents a variable-gain low-noise amplifier (VGLNA) based on an adaptive bias (ADB) circuit for the radar receiver front end. The ADB circuit processes the signal separated by a coupler at the LNA output port. First, the ADB circuit rectifies the coupled signal into positive DC voltage through a rectifier, which is then inverted to control a junction-gate field-effect transistor (JFET). The voltage-controlled current of JFET flows through a voltage-divider network and finally produces the DC biasing voltage for the BJT base termination, which decreases with the increase in the input RF power. The proposed VGLNA operates automatically in high gain at low input power and low gain at high input power, providing a wider dynamic range as compared to the constant-bias counterpart. For validation, a prototype is fabricated and measured at 6 GHz. As observed, the base biasing voltage generated by the ADB circuit is changed from 858 mV to 798 mV as the input power increases from −50 dBm to 0 dBm. As a result, the dynamic range represented by the input P1dB point (IP1dB) has an increase of 6.5 dB, while LNA still maintains a high gain of 15.15 dB at low input power. [ABSTRACT FROM AUTHOR]

This article presents a gate driver circuit with all-magnetic isolation for driving silicon carbide (SiC) power devices in a three-level T-type bridge-leg. Gate driver circuitry for SiC devices has to be tolerant of rapid common-mode voltage changes. With respect to the resultant potentially problematic common-mode current paths, an arrangement of transformers is proposed for supplying the power devices with drive signals and power for their local floating gate driver circuits. The high-frequency carrier phase-switching technique is used to reduce the number of transformers. Signal timing and other implementation issues are addressed when using this arrangement with the T-type converter. The circuit is demonstrated in a 540 V bridge-leg constructed around 650 V and 1200 V cascode-connected normally-on SiC junction field effect transistors (JFETs). [ABSTRACT FROM AUTHOR]

An inertial sensor is a crucial payload in China’s Taiji program for space gravitational wave detection. The performance of the capacitive displacement sensing circuit in the low-frequency band (0.1 mHz to 1 Hz) is extremely important because it directly determines the sensitivity of the space gravitational wave detection missions. Therefore, significant, yet challenging, tasks include decreasing the low-frequency noise in capacitive displacement sensing circuits and improving the capacitive sensing resolution. This study analyzes the noise characteristics of the pre-amplifier circuit within the capacitive sensing circuit, achieves precise tuning of the transformer bridge, and examines how transformer parameters affect noise. In addition, this study introduces a method using a discrete JFET to reduce the operational amplifier current noise and analyzes how feedback resistance and capacitance in TIA circuits affect the overall circuit noise. The proportional relationship between different transformer noises and TIA noise before and after optimization was analyzed and experimentally verified. Finally, an optimized TIA circuit and a superior transformer were utilized to achieve an increase in the capacitive sensing resolution from 1.095 aF/rtHz @ 10 mHz to 0.84 aF/rtHz @ 10 mHz, while improving the performance by 23%. These findings provide valuable insights into further decreasing circuit noise and increasing the capacitive sensing resolution.

Silicon carbide junction field-effect transistors (SiC JFETs) are promising candidates as devices applicable to radiation conditions, such as the decommissioning of nuclear facilities or the space environment. We investigate the origin of the threshold volage (Vth) shift and hysteresis of differently structured SiC JFETs. A large positive Vth shift and hysteresis are observed for a depletion-type JFET with a larger depletion layer width. With changing the sweep range of the gate voltage and depletion width, the Vth shift was positively proportional to the difference between the channel depth and depletion width (channel depth–gate depletion width). By illuminating the sub-band gap light, the Vth of the irradiated depletion JFETs recovers close to nonirradiated ones, while a smaller shift and hysteresis are observed for the enhancement type with a narrower width. It can be interpreted that positive charges generated in a gate depletion layer cause a positive Vth shift. When they are swept out from the depletion layer and trapped in the channel, this gives rise to a further Vth shift and hysteresis in gamma-irradiated SiC JFETs.

Here, we show that silicon carbide (SiC) complementary logic gates composed of p- and n-channel junction field-effect transistors (JFETs) fabricated by ion implantation operate at 623 K with a supply voltage as low as 1.4 V. The logic threshold voltage shift of the complementary JFET (CJFET) inverter is only 0.2 V from 300 to 623 K. Furthermore, temperature dependencies of the static and dynamic characteristics of the CJFET inverter are well explained by a simple analytical model of SiC JFETs. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of $1.8 \mu \text{m}$ and active area of 0.104 mm2 achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98 $\text{m}\Omega \,\cdot $ cm2. The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the ${x}$ -direction and trapezoidal mesas in the ${y}$ -direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ($\vert {V}_{\text{on}}\vert $) and the maximum current before gate junction turn-on (${J}_{\text{umax}}$). The third-quadrant performance can be improved by using forward-on gate voltage, a $\vert {V}_{\text{on}}\vert $ lower than 0.2 V (at 100 A/cm2) and a ${J}_{\text{umax}}$ larger than 500 A/cm2 are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications. [ABSTRACT FROM AUTHOR]

The input transistors (JFETs) of feedback resistor-less charge sensitive preamplifiers (CSPs), for photon and charged particle counting radiation spectrometers, that use semiconductors as their detectors, are operated in an unusual forward biased mode; consequently, manufacturer datasheets cannot necessarily be relied upon, as they do not specify the characteristics of the JFETs when they are operated with the gate-to-source junction forward biased. This experimental study, in which 165 2N4416 and 2N4416A NJ26 silicon junction field effect transistors (JFETs) were electrically characterised at ambient laboratory temperature, focused on the JFETs' performances in the context of their use as input transistors of feedback resistor-less charge sensitive preamplifiers (CSPs). The experimental study found evidence which supports much of the common practice of the skilled CSP designer but which had not been documented with results in the open literature until now. This includes, inter alia, that: the 2N4416 performs better than the 2N4416A; not all transistors even of the same type have comparable performance when operated in forward bias mode; only a small proportion of 2N4416 and 2N4416A transistors are of desirable performance characteristics for CSPs; and, individual screening of each candidate JFET is required if an optimally performing CSP is to be produced – even when using JFETs of the same type from the same batch. The methodology and analysis documented here will also be useful to researchers developing new wide bandgap semiconductor JFETs for high temperature tolerant and radiation-hard CSPs. [ABSTRACT FROM AUTHOR]

We study the inherent ruggedness of the avalanche through the fin channel, a new avalanche mode in a vertical GaN power Fin-JFET, through single-pulse and repetitive avalanche circuit tests. By turning on the gate during avalanche, the major avalanche current path migrates from the p-GaN gate to the n-GaN fin channel. The single-pulse critical avalanche energy density (${E}_{\text {AVA}}$) was measured to be 10 J/cm2, which is the highest reported in GaN transistors. The Fin-JFET withstood over 3700 repetitive avalanche pulses at 70% of ${E}_{\text {AVA}}$. It exhibits a failure-to-open-circuit signature in single and repetitive avalanche. This soft failure mode allows the device to retain its full breakdown voltage, which is highly desirable for system robustness. By contrast, the through-gate avalanche in Fin-JFETs and the reported avalanche in Si and SiC transistors all show a destructive, failure-to-short-circuit signature. These results show the viability of soft avalanche failure in power devices, provide key robustness references for GaN devices, and suggest the fundamental superiority of moving the avalanche path away from the major blocking junction. [ABSTRACT FROM AUTHOR]

An analytical and physical model for the double-gate vertical JFET (VJFET) with a lateral and a vertical channels is presented. The model has been implemented and tested in the SABER circuit simulator and its modeling language, MAST. The model includes an asymmetric representation of the lateral channel which is the main contribution of the paper. The blocking condition depends on both gate voltages. It is a key issue of the VJFET model and it is presented in details. Each junction of the structure is represented as a Shockley pn-junction model in parallel with the associated junction capacitance. The comparison between simulations and experiments yields to satisfying results, both in static and dynamic conditions. The analysis of the remaining difficulties to be solved is given. [ABSTRACT FROM AUTHOR]

In this paper, a varactorless frequency-tuning method for Clapp voltage-controlled oscillator (VCO) design is proposed aiming at increasing frequency-tuning range (FTR) in comparison with the conventional varactor-based counterpart. The proposed structure uses a tunable non-Foster (negative) capacitor (TNC) to sweep oscillation frequency instead of a varactor. The analytical demonstration points that total tuning dynamic (TTD) qualitatively representing FTR is traditionally limited to varactor’s tuning dynamic (TD); while the TNC-based VCO can exhibit very-high TTD, at least over TNC’s TD capacity, if the maximum negative capacitance is appropriately designed, which can tolerate the TD requirement on the tuning component for wideband operation. Circuit realization of TNC is based on a grounded negative impedance inverter (NII) with cross-coupled transistors whose gate voltage controls capacitance. A simulation script using a real discrete transistor model with the realized TNC shows that FTR can be covered with TTD of 2.46 units while the TD of the non-Foster tuning component is only 1.32 units, validating the advantageous operation as well as practical realization possibility of the proposed VCO. In addition, phase noise performance is remained below −100 dBc/Hz for every tuning voltages at 1 MHz offset frequency, while figure of merit comprising FTR effect (FOMT) can be achieved in range of 140-180, which is similar to the existing state-of-the-art VCOs.

This article presents a gate driver circuit with all-magnetic isolation for driving silicon carbide (SiC) power devices in a three-level T-type bridge-leg. Gate driver circuitry for SiC devices has to be tolerant of rapid common-mode voltage changes. With respect to the resultant potentially problematic common-mode current paths, an arrangement of transformers is proposed for supplying the power devices with drive signals and power for their local floating gate driver circuits. The high-frequency carrier phase-switching technique is used to reduce the number of transformers. Signal timing and other implementation issues are addressed when using this arrangement with the T-type converter. The circuit is demonstrated in a 540 V bridge-leg constructed around 650 V and 1200 V cascode-connected normally-on SiC junction field effect transistors (JFETs).

An improved 4H-SiC trench MOS barrier Schottky (TMBS) structure that can significantly reduce the specific on-resistance (Ron,sp) is proposed in this paper. Compared with the conventional TMBS structure, an N-type region is added around the P+ shielding region and along the trench sidewall in the proposed structure, and the doping concentration is higher than that of the drift region. The JFET resistance, and spread resistance can both be reduced significantly during the forward bias to produce a much lower Ron,sp, which have been verified through the numeric simulations and modeling analysis. The critical parameters (N-type region width and its doping concentration) of the proposed structure are mainly optimized by the ATLAS simulation tool. As a result, the breakdown voltage and leakage current of the improved structure remain basically unchanged compared with the conventional TMBS. However, the Ron,sp and FoM (BV2/Ron,sp) can be effectively improved by 41.9% and 70.9%, respectively.

An input stage amplifier is designed for a power operational amplifier based on 70 V high voltage bipolar technology. The amplifier circuit implements a differential telescopic cascode pair using p-type JFETs. It has figure of merits involving low bias current, low offset voltage and current, and high CMRR. The common-collector common-emitter(CC-CE) configuration is used as the load for the input stage circuit in order to reduce the impact resulting from the load and improve the voltage gain as well. Simulation results based on Spectre simulator indicate that the input stage amplifier circuit has achieved 20 pA input bias current,0.11 mV offset voltage and 0.57 fA offset current，while the voltage gain is 89 dB and the unit gain-bandwidth is 8.13 MHz, with the CC-CE load.

This work describes the high-temperature performance and avalanche capability of normally-off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage (VTH) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance (RON) increases from 0.82 at 25 °C to 1.8 mΩ ⋅ cm2 at 200 °C. The thermal stability of VTH and RON are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below 100 μA at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage (BVAVA) with positive temperature coefficient is shown in both the quasi-static I – V sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a BVAVA over 1700 V and a critical avalanche energy (EAVA) of 7.44 J/cm2, with the EAVA comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications. [ABSTRACT FROM AUTHOR]

High-performance and low operating voltage are becoming increasingly significant device parameters to meet the needs of future integrated circuit (IC) processors and ensure their energy-efficient use in upcoming mobile devices. In this study, we suggest a hybrid dual-gate switching device consisting of the vertically stacked junction and metal-insulator-semiconductor (MIS) gate structure, named J-MISFET. It shows excellent device performances of low operating voltage (<0.5 V), drain current ON/OFF ratio (∼4.7 × 10 5 ), negligible hysteresis window (<0.5 mV), and near-ideal subthreshold slope (SS) (60 mV/dec), making it suitable for low-power switching operation. Furthermore, we investigated the switchable NAND/NOR logic gate operations and the photoresponse characteristics of the J-MISFET under the small supply voltage (0.5 V). To advance the applications further, we successfully demonstrated an integrated optoelectronic security logic system comprising 2-electric inputs (for encrypted data) and 1-photonic input signal (for password key) as a hardware security device for data protection. Thus, we believe that our J-MISFET, with its heterogeneous hybrid gate structures, will illuminate the path toward future device configurations for next-generation low-power electronics and multifunctional security logic systems in a data-driven society.

The compact models of junction field effect transistors (JFETs) used in release-quality versions of SPICE-like programs are focused only on the standard temperatures ranging from –60 to 150°C and are unworkable for an electronic circuit design in the cryogenic temperature range (below –120°C). It this study, the Low-T SPICE model of the JFET for designing electronic circuits in the extended temperature range, including the cryogenic range (from –200 to 110°С), is proposed. The model takes into account the changes in the I–V curves caused by the effect of ultralow temperature: growth of the saturation voltage VD sat, decrease of the pinch-off current Ip and steepness BETA, negative slope LAMBDA of the output I–V curves, increase of the drain–source resistance RD as the result of the freezing effect, etc. For this purpose, the dependences of the specified parameters on temperature are introduced in the model. The procedure for extracting the SPICE parameters of the Low-T SPICE model of the JFET is developed according to the results of the measurements of the standard set of the I–V curves in the cryogenic temperature range. The error of the calculation of the I–V curves is not higher than 10–15% in the temperature range from –200 to 110°C. [ABSTRACT FROM AUTHOR]

FinFET is the backbone device technology for CMOS electronics at deeply scaled technology nodes per Moore’s law. Recently, the FinFET concept has been leveraged to develop a new generation of vertical power transistors based on wide-bandgap (WBG) and ultrawide-bandgap (UWBG) semiconductors for kilovolts and high-power applications. The sidewall gate-stack in a vertical power FinFET can rely on either a metal–oxide–semiconductor (MOS) structure or a p-n junction, rendering a Fin-MOSFET or a fin-based junction field-effect transistor (Fin-JFET), respectively. Although the device technologies are still at the early stage of development, 1.2-kV-class WBG gallium nitride (GaN) power Fin-MOSFETs have demonstrated one of the highest static and switching performances in all similarly rated power transistors; UWBG gallium oxide power Fin-MOSFETs have shown high performance up to a breakdown voltage over 2.6 kV. Early UWBG diamond lateral power Fin-MOSFETs have also been demonstrated. Meanwhile, GaN power Fin-JFETs are currently under active development. This article provides a comprehensive tutorial and review of the background and recent advances in WBG and UWBG vertical power FinFETs. It covers fundamental device physics, device and process development, as well as the static and switching performance of various power Fin-MOSFETs and Fin-JFETs. This article is concluded by identifying the current challenges and exciting research opportunities in this very dynamic research field. [ABSTRACT FROM AUTHOR]

A 650-V and 10-A silicon carbide (SiC) stacked cascode assembly has been proposed and demonstrated, in which a low-voltage Si-MOSFET (LV Si-MOSFET) is stacked on a high-voltage SiC buried gate static induction transistor (HV SiC-BGSIT). This is achieved by mounting Al bumps on the source pad of the HV SiC-BGSIT die and inserting a stacked Ag paste/epoxy layer between the HV SiC-BGSIT die and LV Si-MOSFET die. The epoxy layer is used to electrically separate the wire bonded on the gate pad of the HV SiC-BGSIT from the bottom electrode of the LV Si-MOSFET. The results of the measured static characteristics at temperatures from room temperature to 400 K and hard switching characteristics at room temperature of the fabricated stacked cascode sample verify that the proposed stacked cascode assembly successfully performs as a SiC cascode switching device. Thus, the proposed assembly contributes to the reduction in the footprint and parasitics for the conventional discrete packages and modules using the SiC cascode configuration. [ABSTRACT FROM AUTHOR]

The proposed work covers the tasks of such areas as reducing input currents and bias voltage of integrated operational amplifiers (ICs OA) manufactured according to BiFET technology, the prospect of using JFET transistors in digital circuit technology, Si CMOS technology at 22 nm node and beyond, manufacturing bipolar transistors on ultrathin layers of the active base and emitter, increasing resistance of ICs to external influences. The main method of experimental investigation of channeling is the construction of impurity distribution profiles using SIMS. In this work to study the channeling effect of boron and phosphorus in silicon was chosen the method for constructing the response surface of the saturation current of JFET for a silicon wafer. The choice of method was based on the high sensitivity of the cut-off voltage and saturation current of the JFET transistor to the channel thickness and impurity concentration in it, the relative simplicity of performance and practical benefits in improving BiFET technology. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) super-junction JFET was designed, simulated and fabricated through trench-etching and sidewall-implantation technology, which avoids the expensive epi-regrowth process. The fabricated super-junction JFET achieves a breakdown voltage of 1000V with specific on-resistance of 1.3m $\Omega ~\cdot \text {cm}^{{2}}$. The threshold voltage (${V}_{\text {th}}$) is stable over a wide range of temperature with less than 0.2V shift from 25°C to 175°C. These results demonstrate that the trench-etching and sidewall-implantation technology is a promising option to fabricate SiC super-junction devices. These devices could have great potential for future power electronics. [ABSTRACT FROM AUTHOR]

The state-of-the-art superjunction (SJ) MOSFETs are based on the p-n pillar structures, arranged in a 2-D stripe geometry. This arrangement uses the superposition of the electric field components at the p-n junctions to create an enhanced depletion volume for higher breakdown capability. In this article, we will discuss structures, which additionally use the component of the electric field in the third dimension, to further enhance the depletion space. This allows higher doping concentrations in the pillars, which result in a better tradeoff between the breakdown voltage and the ON-state resistance, when compared with the 2-D structures. Specifically, we present a core–shell cylindrical SJ structure, and using the radial Poisson equation, we explain the electric field distribution within the SJ. We further discuss which geometry (core or shell) gives the best performance tradeoff. This is followed by the development of an analytical model, for the ON-state resistance in a 3-D SJ. Finally, we derive a specific figure of merit for the 3-D SJs and compare it with that of the equivalent 2-D structures. [ABSTRACT FROM AUTHOR]

High temperature characteristics of bipolar-mode operation of normally-off diamond junction field-effect transistors were investigated up to 573 K. As an important factor, the current gain depending on the gate current was analyzed with a theoretical model. We found that the experimental current gain decreased with the rise in the gate current, in agreement with the theoretical estimation considering the recombination at the end regions. We achieved 4-9 times higher drain currents in the bipolar-mode compared with the unipolar-mode operation at a DC current gain of 10. Furthermore, the bipolar-mode currents at the high temperatures of 473 and 573 K became two orders of magnitude larger than the unipolar-mode current at room temperature with a large DC current gain of 102.

Based on the invalidation and damage of the field effect transistors under lightning radiation, we establish the breakdown experiment with open-circuit voltage wave and the protection experiment with TVS as the protection device. The junction field effect transistor and the metal oxide semiconductor field effect transistor are used as material. We draw some conclusions. In the breakdown experiment, the breakdown voltage of the MOSFETs is higher than that of the JFETs as a whole. The MOSFET can be adopted in the amplifier circuit which is expected to get higher input resistance and breakdown voltage. The drain-source resistance can recover to the original resistance value after being placed a period of time, but the gate-source resistance is irreversible. The invalidation of the device under test is due to the breakdown of gate-source. The TVS can protect the FTEs well. The change of pin resistance of the MOSFET is inconspicuous. MOSFETs are more stable for debugging and development of the amplifier circuit. The results provide some significance for the development and improvement of the lightning electric fields change measuring instruments in the future. [ABSTRACT FROM AUTHOR]

An analytical model for superjunction (SJ) MOSFETs having an oxide pillar between the n-pillar and the p-pillar is developed. Owing to the low permittivity of the oxide, a high electric field is sustained across the oxide. This reduces the parasitic depletion width within the n-pillar, thus improving the current conducting path. The advantage of this structure is particularly visible as the cell pitch is scaled down and the pillows become narrower. The use of an oxide pillar leads to 30% reduction in the specific ON-state resistance when compared to a conventional SJ for a 2- $\mu \text{m}$ cell pitch. The analytical model shows a good agreement with the simulation results. [ABSTRACT FROM AUTHOR]

Abstract In the future ATLAS Inner Tracker detector (ITk), several silicon strip modules will be biased by a single High-Voltage (HV) line, so that a switch between each strip sensor and the HV line is required to disconnect faulty sensors. Such a switch must satisfy strict requirements, such as being radiation hard, being able to sustain high voltages in the OFF state and being able to operate in a high magnetic field. At Brookhaven National Laboratory we conceived a new kind of solid-state switch that can potentially meet all the specs: it is a HV silicon vertical JFET. Before designing and fabricating the JFET, we did a study using numerical TCAD simulations that demonstrate the feasibility of fabricating the device in a standard planar technology. We report such simulations, highlighting in particular a few key parameters to which the JFET performances are most sensitive. [ABSTRACT FROM AUTHOR]

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In this letter, we report an analytical model for the on-state characteristics of a superjunction (SJ) metal–oxide–semiconductor field effect transistor, featuring a compensated pillar between the n-pillar and the p-pillar. Since a large amount of lateral electric field is sustained in the compensated region, the doping concentration in the n-pillar can be enhanced significantly, leading to a substantial reduction in the on-state resistance of the SJ. Simulation results proved that the use of an extra compensated pillar within the SJ structure reduces the on-state resistance by 25% compared to that of a conventional SJ for the same breakdown voltage. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)