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SU-8 is an epoxy-based, negative photoresist that is widely used in the manufacturing of micromechanical systems. The polymer cross-linking that occurs during the photolithographic processing of SU-8 can result in high levels of stress in the patterned film. This has significant implications for the yield and reliability of SU-8 structures and needs to be understood if the material is to be integrated with other technologies. This paper describes micromechanical test structures that provide the opportunity to wafer map the stress in SU-8 at different stages of the process. The structures are fabricated in a thick layer of SU-8 and are subsequently released from the underlying substrate using a dry chemical vapor etch process. An automated optical measurement system has been built to allow rapid optical inspection of many thousands of test structures fabricated on 200 mm wafers. Initial results indicate significant tensile stress in the SU-8, which demonstrates a radial variation along with a dependence on the process conditions.

Silicon based integrated circuit technology has shown astonishing progress scaling to smaller geometries as the industry follows Moore's predictions. However, in recent years the cost associated with staying at the leading edge of silicon IC technology has resulted in many companies being either unable, or unwilling, to afford the investment required. As a consequence some have decided to use foundry technology and/or diversify into new device types and associated novel application areas. All of these diverse Silicon + technologies have one particular feature in common, namely they all use silicon as a platform for system integration with the added value being the innovation associated with post-processing and/or technology integration, which in many cases is realised on standard foundry technology. This paper examines many of the issues associated with integrating foundry and custom IC wafers with both new materials and technologies such as MEMS based sensors and actuators. In particular it examines the various options available for companies considering Silicon + technology applications and presents examples of successful applications of this approach. Some of these are illustrated below.

This paper compares electrical, optical, and atomic force microscope (AFM) measurements of critical dimension (CD) made on a chrome on quartz photomask. Test structures suitable for direct, on-mask electrical probing have been measured using the above three techniques. These include cross-bridge linewidth structures and pairs of Kelvin bridge resistors designed to investigate dimensional mismatch. Overall, the results show very good agreement between the electrical measurements and those made with a calibrated CD-AFM system, while the optical metrology system overestimates the measured width. The uncertainty in each of the measurements has been considered, and for the first time an attempt has been made to describe the levels and sources of uncertainty in the electrical measurement of CD on advanced binary photomasks.

This paper presents a robust anodic Ta2O5 dielectric as an alternative insulator for fabricating low-voltage electrowetting on dielectric (EWOD) systems. Previously reported low-voltage EWOD technologies require high-temperature processes ( > 435degC), which unlike this room temperature technology, are not compatible with standard copper and aluminum integrated circuit interconnect technology as well as polymer-based substrates. The anodized Ta2O5 forms a uniform pinhole free layer with a surface roughness (R a) of 0.6 nm. This robust film enables an ultrathin amorphous FluoroPolymer layer to be employed to reduce the EWOD driving voltage to 13 V. Both sub-20-nm Teflon-AF and CYTOP layers have been successfully coated on top of Ta2O5 with good adhesion. Applying voltages of 6-15 V significantly modified the contact angles of droplets in air on these samples (121deg to 81deg on Teflon-AF at 13 V and 114deg to 95deg on CYTOP at 6 V). Successful 14-V EWOD manipulation involving droplets being dispensed from a reservoir, their movement, followed by merging them together has been demonstrated using devices using a Teflon-AF + Ta2O5 dielectric.

Test structures have been fabricated to allow electrical critical dimensions (ECD) to be extracted from copper features with dimensions comparable to those replicated in integrated circuit (IC) interconnect systems. The implementation of these structures is such that no conductive barrier metal has been used. The advantage of this approach is that the electrical measurements provide a nondestructive and efficient method for determining critical dimension (CD) values and for enabling fundamental studies of electron transport in narrow copper features unaffected by the complications of barrier metal films. This paper reports on the results of tests which have been conducted to evaluate various extraction methods for sheet resistance and line width values from the current design.

This paper presents a comparison of optical and electrical techniques for critical dimension (CD) metrology on binary and alternating aperture phase-shifting masks. Measurements obtained from on-mask electrical CD structures are compared with optical measurements made using a deep ultraviolet mask metrology system. The results show that the presence of alternating phase-shifting trenches between the chrome blocking features has a detrimental effect on the optical measurements and that this effect strongly depends on the depth of the trenches. In addition, the optical metrology system appears to have problems with the measurement of the narrowest isolated features due to calibration related issues. Electrical CD measurements are seen as a way of probing the limits of optical tool calibration and for highlighting and managing the need to extend the complexity of the calibration schedule.

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Omega have been obtained from via chain test structures and an average specific contact resistivity of 1.7 X 10-8 Omega cm2, measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

Optical fibre pressure sensors have potential performance advantages over electrical sensors in measuring rapid transients such as shock waves from explosive blasts. We report the development of micromachined optical fibre Fabry–Perot pressure sensors using a silicon dioxide or nitride diaphragm and detail the fabrication stages of the sensor body and diaphragm. The planar technology used is based on silicon deep etching and direct fusion bonding of silicon wafers. Test results for both types of diaphragm are presented. Sensors with rise times better than 3 µs, range 0.1 to 1 MPa and resolution ~500 Pa have been demonstrated in explosives trials. Despite the difference in the sign of stress for the two diaphragm types, both demonstrated excellent high-speed response to explosively generated air shocks.

This paper reports the first direct experimental measurement of electromigration-induced stress in aluminum interconnects, using a series of microrotating stress sensors. The build-up of stress gradients in interconnect metallization, which is concomitant with backstress, has been previously investigated theoretically, but experimental verification using optical or X-ray techniques has proven more difficult. These initial results show a compressive-stress gradient along the line of stress sensors, consistent with that predicted by conventional mass-transport theory. Additionally, these measurements are in qualitative agreement with the mathematical model proposed by Korhonen et al. (1993), with a reduced-stress and increased-diffusion coefficient. These differences are discussed, and the causes postulated. The limited resolution of previous techniques restricts their ability to obtain a detailed characterization, whereas, in principle, this new technique can be scaled to the end of the International Technology Roadmap for Semiconductors. These preliminary findings suggest that the presented technique will provide a valuable tool for the investigation of back-end-of-line interconnect stress in the future.

This paper presents work on the development, fabrication and characterization of a suspended Greek cross measurement platform that can be used to determine the sheet resistance of materials that would contaminate Complementary Metal Oxide Semiconductor (CMOS) processing lines. The arms of the test structures are made of polysilicon/silicon nitride (Si/sub 3/N/sub 4/) to provide a carrier for the film to be evaluated and thick aluminum (Al) probe pads for multiple probing. The film to be evaluated is simply blanket deposited onto the structures and because of its design automatically forms a Greek cross structure with (Al) probe pads. To demonstrate its use, 1) gold (Au), 2) copper (Cu), and 3) silver(Ag) loaded chalcogenide glass Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ have been blanket evaporated in various thicknesses onto the platform in the last processing step and autopatterned by the predefined shape of the Greek crosses. The suspension of the platform ensured electrical isolation between the test structure and the surrounding silicon (Si) substrate. The extracted effective resistivity for Au (5.1/spl times/10/sup -8/ /spl Omega//spl middot/m), Cu (1.8- 2.5/spl times/10/sup -8/ /spl bsol/ /spl Omega//spl middot/m) and Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ (2.27/spl times/10/sup -5/ /spl Omega//spl middot/m-1.88 /spl Omega//spl middot/m) agree with values found in articles in the Journal of Applied Physics (1963), the Journalof Physics D: Applied Physics (1976), and the Journalof Non-Crystalline Solids (2003). These results demonstrate that the proposed Greek cross platform is fully capable to measure the sheet resistance of low (Au, Cu) and high Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ resistive materials.

This paper uses a rotating-beam-sensor structure to show that the extrinsic stress from the mismatch in expansion coefficient between the aluminum and the silicon substrate dominates over the compressive stress from the sputter growth. Sintering the layers at temperatures above 150/spl deg/C reduces this compressive stress due to the action of creep. Calibration of the rotation of the device has been undertaken by direct comparison to high resolution X-ray-diffraction measurements and these show that the sensor has a resolution better than 2.8 MPa. Furthermore, we have used the sensor to investigate the variation of in-plane stress with the compliance of the intermetal dielectric, by directly comparing sensors fabricated on SiO/sub 2/ and polyimide layers.

The evaluation of stress in sub-micron tracks is critical for the microelectronics industry and there is a need for new methods of measurement. This paper advocates the use of a rotating beam sensor structure which can be fabricated on the wafer along side electronic devices and used to monitor stress generation and relaxation as a function of processing. The rotation can be observed with a reflected light microscope and correlated to the actual stress level. Several samples, assputtered and sintered, were prepared with the aim of having different residual stress states. X-ray diffraction with a low incident angle geometry, was used to evaluate the residual stresses on the aluminum layer. Computer simulations using ANSYS were also performed in order to correlate the sensor rotation with the experimental stress values. It was observed that the extrinsic stress from the mismatch in expansion coefficients between the aluminum layer and the silicon substrate dominates over the compressive stress from the sputter growth. Sintering the layers at temperatures above 150°C reduces this compressive stress due to the action of creep. The calibration of the rotation of the device with the direct measurements of the X-ray diffraction shows that the sensor has a resolution better than 2.8 MPa.

Atomic force and scanning electron microscope measurements of electrical structures for the measurement of critical dimension on alternating aperture phase shifting masks are presented. These have been used to explain anomalies that were observed in previously reported work. In addition, the development of a new capacitance test structure which can measure the alignment between the chrome blocking layer and the phase shifting areas etched into the quartz mask substrate is presented. A progressional offset array technique enables the use of this test structure without calibration and this is demonstrated by simulation and measurements.

The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes.

This paper reports the latest design and the associated fabrication technology of the Mk II prototype infrared (IR) detector for the two 5120 pixel SCUBA-2 (submillimetre common user bolometer arry) instruments, which are to be mounted on the James Clerk Maxwell telescope (JCMT) in Hawaii. Progress is described on the design and the technology modules being developed for the new detector, which is based upon silicon micromachining. The two arrays of transition edge sensors (TES) are used to detect incoming radiation with wavelengths of 450 and 850 μ respectively and as the SCUBA-2 detector operates at about 100 mK, it consequently involves integration with low-temperature electronics and careful design of the associated interconnect. A key aspect of the connection between the TES detector and readout electronics is the use of indium flip-chip bumps, which become superconducting at cryogenic temperatures. The integration of nanoscale membranes and transition edge sensors together with microsystem technology enables SCUBA-2 to have of the order of 10 -17W (1 Hz bandwidth) sensitivity to incoming radiation.

The dependence of residual stress on the process parameters for aluminum metallization has been studied using a rotating beam sensor. This shows increasing tensile stress with both the target power and ambient pressure used during the sputter deposition of the aluminum layer. The bulk resistivity of the deposited aluminum has been measured using a Van der Pauw technique on test structures fabricated alongside the sensors and this shows different trends with respect to the target power and ambient pressure. This indicates that the stress in an interconnect feature is dominated by extrinsic components, which result from the mismatch in thermal expansion coefficient between the constituent layers, rather than the defects formed during the sputter deposition of the metallization. This indicates the suitability of the stress sensor technique to the monitoring of interconnect features in a production line environment.

This paper presents work on the analysis of the effect of Joule heating on sheet resistivity measurements using Greek cross test structures. As part of this work, design rules have been derived to minimize the heating effect associated with currents forced during their measurement. To accomplish this, finite-element (FE) simulations were employed to identify the location of heat generation and cooling mechanisms in the structures. This identified that the temperature could be minimized by: firstly, decreasing cross arm length, and therefore both electrical and thermal resistance of the arms; and secondly, by integrating pads and leads to improve the heat sink effect. These results were confirmed by sheet resistance measurements of four different Greek cross designs which demonstrated that the proposed design rules reduced the Joule heating effects on the sheet resistance measurements by up to 25%.

A novel process is presented which produces platinum features using direct UV exposure of the photosensitive organometallic material. The technique reduces the number of process steps involved when creating a metal pattern on a substrate by not requiring photoresist, solvents, or etch processes. In contrast to processes already reported in the literature, the method is compatible with microelectronic processes and does not require costly special equipment. Two test chips with MOS capacitors and resistive structures fabricated using the new organometallic material have been characterized. The results show that the deposited films are metallic and have a good adhesion to silicon dioxide. The work function of the platinum films is in agreement with the value found in the literature, but the measured resistivity and XPS indicate that the metal film contains some remaining organometallic residue after pattern development.

The design and fabrication is described of the prototype IR detector for the SCUBA-2 80×80 pixel array (Submillimetre Common User Bolometer Array), which is to be mounted on the James Clerk Maxwell Telescope in Hawaii. The detector technology is based on silicon micromachining, with transition edge sensors (TES) being used to detect incoming radiation with wavelengths of 450 and 850 μm. Each TES is located on a λ/4 silicon brick suspended on a silicon nitride membrane and supported by a silicon micromachined waffle. Low-temperature indium bump bonding connects each TES to a SQUID multiplexer chip. The paper details the design considerations and the technology used to fabricate the detector wafer.

The process-induced stress in interconnect structures in modern integrated circuits has a direct influence on the mean time to failure for the device. As the active devices are aggressively scaled to meet the constant demands of the industry, the interconnect structures are also being driven to smaller dimensions and this is increasing the demands made on material scientists to deliver high quality, stress-free metallization. We have demonstrated the measurement of process-induced stress in a single interconnect structure, fabricated in a CMOS compatible process, using a rotating beam sensor. We have shown its applicability in observing the variation in stress level from differing process conditions. Comparison of the rotation observed in the fabricated sensors with finite element simulation using ANSYS is discussed. The structure is suitable for use in a production environment and is scalable to deep sub-micron features for future technology nodes.

The effects of the barrier layer and dishing in copper interconnects lead to extra difficulties in measuring sheet resistance (R/sub S/) and linewidth when compared with equivalent measurements on nondamascene tracks. This paper examines these issues and presents the results of simulations that quantify the effects of diffusion barrier layers and dishing on the extraction of R/sub S/ from cross type test structures and the effect this has on linewidth measurement.

Mobile communication is becoming increasingly ubiquitous. Portable devices need to be equipped with displays that are capable of presenting an ever-growing quantity of information to the viewer at high resolution. Microdisplays based on ferroelectric liquid crystal-over-silicon (FLCoS) technology provide an attractive solution. They are fast, small, lightweight and — being mostly based on standard CMOS technology — should be available at low cost. In this article we report on recent advances in the manufacturing process of FLCoS microdisplays.

Results are presented on the use of null wire segment holograms for the in-line assessment of mask alignment errors in the integrated circuit fabrication process. Process variations are detected by measuring the light intensity generated by a hologram designed to project a null image. To detect alignment errors, the mask for the wire segment hologram (WSH) is distributed between two mask layers. If the two sets of diffracting structures defined by the masks are transferred to the wafer with perfect registration, the result is an area of light cancellation (null) in the image plane. Increased mask misalignment leads to imperfect wavefront cancellation, which is manifested as an increase in light intensity in the null region. In order to characterize misalignment under controlled conditions, the two portions of the holographic test structure were initially recombined into a single structure but with intentional misalignment between the two portions designed into the mask. The technique was then used to characterize the alignment errors between two separate masks with the actual fabricated offsets measured using atomic force microscopy. Initial results indicate the technique is capable of resolving 0.1-/spl mu/m mask misalignment for a 1-/spl mu/m minimum feature process.

This paper investigates the feasibility of direct Al-Al contact using low temperature wafer bonding process for the integration of MEMS and CMOS devices. Sufficient mechanical strength oxide-oxide bonds can be achieved using an oxygen plasma assisted low temperature wafer bonding process, with Al structures present on the bonding surface. An average contact resistance of 2.6i?10-8?cm2 was measured from single contact test structures, indicating that the establishment of direct Al-Al interconnect during the bond anneal step is possible.

Theoretical and experimental results using computer generated wire segment holograms for statistical interconnect metrology are presented. Test structures have been constructed using a process capable of imaging 1-/spl mu/m features and consist of arrays of wire segments illuminated by a He-Ne Laser. Since the holograms are fabricated at the same time as actual wires on the wafer, the quality of the projected image correlates with the emergence of global feature patterning errors. Specifically, this paper presents data on the effect of varied exposure time on the intensity of the projected image. An initial statistical analysis indicates that the test structures are capable of detecting variations in wire geometry which are approximately 1.0% of the nominal wire width. It is anticipated that significant improvements to this level of sensitivity can be obtained by optimization of the holographic encoding process and test image selection.

Prototype imaging subarrays for SCUBA-2 (the Submillimeter Common-User Bolometer Array) have been fabricated and tested. The pixel count (1280) of these wafer-scale imagers is significantly larger than any other low-temperature detectors produced to date, and represents a major step forward for the low-temperature detector community. These transition-edge-sensor (TES) based imagers utilize several innovations including in-focal-plane superconducting quantum intereference device (SQUID) multiplexers, micromachined Si block absorbers, and superconducting wafer hybridization. In this paper, we review the fabrication processes developed for these imagers and present recent optical data from a prototype imaging subarray.

This paper presents the simulation and experimental measurements of an electrical test structure that can be used to assess the degree of planarization of interlayer dielectrics. It consists of two sets of metal combs separated by a dielectric. For each structure the combs on the two layers overlap each other, with adjacent structures having the overlap in one direction progressionally offset by 0.2 /spl mu/m. The capacitance of these structures is then measured, from which the degree of planarization can be assessed. This structure has potential applications for characterising chemical mechanical polishing (CMP) processes for multilevel very large scale integration (VLSI) applications.

This paper reports the development of processing methods and test structures for the characterisation and evaluation of Parylene-C as an insulating structural layer material for integration with planar micro-inductors. The process involves the filling of high aspect ratio gaps between copper structures with Parylene and subsequent chemical mechanical planarisation. A test chip has been designed to characterise this process and the results presented. Subsequently complete micro-inductors, with magnetic cores, have been fabricated to demonstrate the capability of the process.

An improved bottom-up electroplating technique has been successfully developed for the fabrication of TSV arrays with 9.5:1 aspect ratios. 125,500 TSVs have been fabricated in an area of 6×6 cm with a horizontal and vertical pitch of 240 μm. A method of visually inspecting the via yield is presented, and Kelvin test structures and contact chain test structures have been fabricated to electrically evaluate single and multiple TSVs respectively. The average resistance of the Cu vias was measured as of 9.1 mΩ using the Kelvin contact resistance structures.

The laser-plasma X-ray source at the Rutherford Appleton Laboratory has been used in a series of preliminary lithography trials in order to establish the feasibility of using this source for deep submicron device fabrication. These trials have provided a demonstration of photoresist linewidths down to 130nm and functional silicon FETs have been produced with 200nm gate electrodes. These devices show peak transconductances of 220mS/mm and 100mS/mm for n-channel and p-channel cases respectively. This paper summarises the lithographic procedures and resulting device characteristics.

The laser-plasma X-ray source at Rutherford Appleton Laboratory was operated at ∼1nm wavelength and 100mW average power for proximity printing of 180nm wide lines into 0.5μm thick photoresist. The resist process was used to define the gate electrode into polysilicon.

This paper presents details of the design and fabrication of test structures specifically designed for the characterization of two distinct digital microfluidic technologies: electro-wetting on dielectric (EWOD) and surface acoustic wave (SAW). A test chip has been fabricated that includes structures with a wide range of dimensions and provides the capability to characterize enhanced droplet manipulation, as well as other integrated functions. The EWOD and SAW devices have been separately characterized first of all to determine whether integration of the technologies affects their individual performance, including device lifetime evaluation. Microfluidic functions have then been demonstrated, including combined EWOD/SAW functions. In particular, this paper details the use of EWOD to anchor droplets, while SAW excitation is applied to perform mixing. The relationship between test structure designs and the droplets anchoring performance has been studied.

A test structure is described which can be used to optimize the focus of wafer steppers. Simulation is used to examine the effect that some of the design parameters have on the sensitivity of the structure. Finally some practical measurements are presented. >

Today's Optical Proximity Correction (OPC) is becoming increasingly complex and necessitates that we use smaller and smaller grid sizes to produce the fine patterns required. These small grids lead to significant overhead in data handling and, more importantly, for the tools that will write and inspect the mask, together making the mask extremely expensive. For two dimensional structures, such as corners, we have very complex structures using either additive or subtractive OPC features to produce the desired shape. However, it is unclear whether these structures need to be so perfect for the electrical task they are intended to perform. In previous work we have created a number of corner type electrical test structures and applied varying degrees of OPC to both the outer and inner corners of the structures, then printed these on doped polysilicon and the electrical effect of the OPC was investigated. This work showed that the electrical effect of OPC on the outer corner was minimal, whereas the inner corner shape had a marked influence upon the electrical resistance of the circuit feature. However, technology continues to move forward and polysilicon gates are being replaced by metal gates for 32nm node. Therefore, in this work we replace the polysilicon with a metal and investigate the size and position of OPC applied to both the outer and inner corners of the structures. The data obtained using the metal structures suggests that as was the case when using polysilicon, OPC on the outside corner has little impact upon a simple circuit's performance, while care should be taken with OPC on the inner corners, particularly with regard to the size of the OPC serifs used.

Electrical test structures for the characterisation of Optical Proximity Correction (OPC) have been fabricated in thin aluminium using i-line lithography and reactive ion etching. Initial electrical measurements are presented which show an increase in the resistance of a right angled section of Al track as the level of OPC on the inside corner is increased. Structures with OPC applied to the outer corner do not show the same change in resistance. SEM images of similar Al test structures clearly show the effects of applying OPC and suggest that inner corner serif OPC leads to a narrowing of the conducting track.

SU-8, an epoxy based negative photoresist, is widely used in the manufacture of micromechanical systems but can exhibit significant levels of stress build-up during processing. This paper describes micromechanical test structures that provide the opportunity to spatially characterise stress the in SU-8 at different stages of the process. The structures are fabricated in a thick layer of SU-8 and are subsequently released from the underlying substrate using a dry chemical vapour etch process. The initial results indicate that there is significant tensile stress in the SU-8, and that this demonstrates a radial variation along with a dependence on the process conditions.

Previously reported suspended microrotating test structures designed to measure the stress in thick layers of electroplated Permalloy (NiFe alloy) have been analysed using finite element modelling and compared with experimental measurements. These results have been used to optimise a stress sensor test structure and design a new mask, with an array of test structures specifically designed to wafer map the stress of thick nickel and Permalloy films. This is the first time these structures have been employed for determining spatial variation in film stress and the results of this characterisation are reported for nickel.

Today's Optical Proximity Correction (OPC) is becoming increasingly complex and necessitates using smaller and smaller grid sizes to produce the fine patterns required. These small grids lead to very high overhead in data handling, as well as for the tools that will write and inspect the mask; which together make masks extremely expensive. For two dimensional structures such as corners, we use complex structures incorporating either additive or subtractive OPC features to produce the desired shape. It is unclear though, how precisely the final structures must match the original design to perform their intended electrical functions. In this work we have created a number of corner type electrical test structures and applied different degrees of OPC to both the outer and inner corners of the structures. These features were then printed on doped polysilicon wafers, and the wafers were etched and electrically tested. The electrical effect of OPC on the outer corner was found to be minimal, whereas the inner corner shape had a significant effect upon the electrical resistance of the circuit feature. The data suggests that OPC on the outside corner has little impact upon a simple circuit's performance, but care should be taken with OPC on the inner corners, particularly with regard to the size of the OPC serifs used.

The effects of the GHOST proximity correction process on chrome-on-quartz photomasks can prove difficult to quantify and so they are not routinely characterised. This paper presents a methodology for addressing this issue using electrical test structures designed to measure dimensional mismatch. In the past these have been used successfully to characterise standard GHOSTed photomasks, which displayed systematic offsets that were not seen on an unGHOSTed mask using the same design. In order to investigate this further, a second mask was fabricated using a variation of the GHOST process which increased the resolution of the secondary exposure to be the same as the primary pattern. This enabled the source of the previously observed systematic offset to be determined as test structures on the new mask did not show the same overall dimensional bias. However, the range of mismatch in some of the structures was increased as a result of the new process.

Electrical test structures have been designed to enable the characterisation of corner serif forms of optical proximity correction. These structures measure the resistance of a conducting track with a right angled corner. Varying amounts of OPC have been applied to the outer and inner corners of the feature and the effect on the resistance of the track investigated. A prototype test mask has been fabricated which contains test structures suitable for on-mask electrical measurement. The same mask was used to print the structures using an i-line lithography tool for on-wafer characterisation. Results from the structures at wafer level have shown that OPC has an impact on the final printed features. In particular the level of corner rounding is dependent upon the dimensions of the OPC features employed and the measured resistance can be used to help quantify the level of aggressiveness of the inner corner serifs.

An approach is presented to reduce the number of pads required by electrical test structures by using a multiplexed interconnect scheme. This passive multiplexed scheme requires only two levels of interconnect and can be used for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks. The basic measurement procedure to access individual components is to force a voltage on one of the access pads and then ground one of the group terminals via an ammeter. While an even number of pads is not mandatory it is recommended since this maximizes the efficiency of pad usage. >

A wireless power transfer and communication system based on near-field inductive coupling has been designed and implemented. The feasibility of using such a system to remotely control drug release from an implantable drug delivery system is addressed. The architecture of the wireless system is described and the signal attenuation over distance in both water and phosphate buffered saline is studied. Additionally, the health risk due to exposure to radio frequency (RF) radiation is examined using a biological model. The experimental results demonstrate that the system can trigger the release of drug within 5 s, and that such short exposure to RF radiation does not produce any significant (

This paper presents results from the use of electrical measurements to investigate dimensional mismatch in an advanced photomask process. Test structures consisting of matched pairs of Kelvin resistors have been measured and the results analysed to obtain information about the capability of the mask making process. The mask plate used in this work has an array of over 350 sets of mismatch test structures, providing an unprecedented volume of data. A second mask, which was underexposed, has allowed the relationship between mismatch and the location of nearby mask writing pattern boundaries to be investigated for the first time.

This paper evaluates test structures designed to characterise electrical contacts between interconnect on bonded wafers. Both simulation and experimental measurements are used to explore the capability of a stacked Greek cross type test structure to extract the contact resistivity (pc) between two bonded conductive layers. It is concluded from the simulations and actual electrical measurements of the benchmark Kelvin structures that the stacked Greek cross can only be used where there is a relatively high specific contact resistivity. For the structures evaluated in this study, this was found to be greater than pc > 9.0 x 10-7 Omega-cm2.

This paper reports the measurement results from a set of electrical, on-mask test structures based on industry standard test feature layouts normally used to investigate process proximity effects and improve optical proximity correction (OPC) models. The electrical test structures were fabricated on a binary photomask using the GHOST proximity correction technique to compensate for typical e-beam induced proximity errors. This is one of the first times that electrical test structures have been used to evaluate GHOST exposure. The test structures were measured electrically and optically with a dedicated photomask metrology tool and the results from the two techniques are presented.

This paper compares electrical, optical and AFM measurements of critical dimension (CD) made on a chrome on quartz photomask. Test structures suitable for direct, on-mask electrical probing have been measured using the three techniques and the results show very good agreement between the electrical measurements and those made with a calibrated CD-AFM system.

The development of an implantable system designed to deliver drug doses in a controlled manner over an extended time period is reported. Key performance parameters are the physical size, the power consumption and also the ability to perform wireless communications to enable the system to be externally controlled and interrogated. The system has been designed to facilitate wireless power transfer, which is very important for miniaturisation as it removes the need for a battery.

This paper describes the design and measurement of electrically measured test structures for the characterisation of dimensional mismatch in an advanced photomask making process. Test structures consisting of pairs of Kelvin connected bridge resistors have been fabricated on a chrome-on-quartz photomask plate. These have been electrically measured on-mask and the results used to obtain information about dimensional mismatch in the mask making process.

The standard approach to generate the data required for automated proximity correction is to measure a set of patterned features using an optical tool or a critical dimension scanning electron microscope (CD-SEM). This paper describes the design of a set of on-mask electrical test structures to perform the same task which has a number of attractions. The electrical test structures are based on the Kelvin bridge resistor to measure the widths of isolated and densely packed lines and spaces. The results from these measurements can be used to extract information about proximity effects in the mask making process and to generate rules or models for the correction of mask designs. Electrical results from a test mask, fabricated without any correction for e-beam proximity effects, are presented and compared with optical measurements of the same structures made with an industry standard mask metrology tool.